Used to bind component instances to design entities and collect architectures to make, typically, a simulatable test bench. One configuration could create a functional simulation while another configuration could create the complete detailed logic design. With an appropriate test bench the results of the two configurations can be compared.
Note that significant nesting depth can occur on hierarchal designs. There is a capability to bind various architectures with instances of components in the hierarchy. To avoid nesting depth use a configuration for each architecture level and a configuration of configurations. Most VHDL compilation/simulation systems allow the top level configuration name to be elaborated and simulated.
Syntax:
configuration identifier of entity_name is
[ declarations , see allowed list below ]
[ block configuration , see allowed list below ]
end configuration identifier ;
To understand configuration in depth let us consider below entity and architectures,
Entity E1 is
end E1;
Architecture A1 of E1 is
end Architecture A1;
Architecture A2 of E1 is
end Architecture A2;
Architecture A3 of E1 is
end Architecture A3;
Entity E2 is
end E2;
Architecture A1 of E2 is
Component E1;
begin
L1: E1 port map ();
L2: E1 port map ();
end Architecture A1;
Architecture A2 of E2 is
begin
behavioural discription;
end Architecture A2;
Entity E3 is
end E3;
Architecture A1 of E3 is
Component E1;
Component E2;
begin
L1: E1 port map ();
L2: E2 port map ();
L3: E2 port map ();
L4: E1 port map ();
end Architecture A1;
Architecture A2 of E3 is
begin
behavioural discription;
end Architecture A2;
Below is the detailed configuration for entity E3;
Configuration C1 of E3 is
for A1
for L1 : E1
use entity work.E1(A1);
end for;
for L2 : E2
use entity work.E2(A2);
end for;
for L3 : E2
use entity work.E2(A1);
for A1
use entity work.E1(A2);
end for;
end for;
for L4 : E1
use entity work.E1(A3);
end for;
end for;
end Configuration C1;
