Built-in Primitives

 

Formal Definition

The built-in primitives provide a means of gate and switch modeling.

Simplified Syntax

For and, nand, or, nor, xor, xnor, buf, not

  gate (drive_strength) #(2delays) instance_name[range] (list_of_ports);

For bufif0, bufif1, notif0, notif1

  gate (drive_strength) #(3delays) instance_name[range] (list_of_ports);

For nmos, pmos, rnmos, rpmos, cmos, rcmos, rtranif0, rtranif1, tranif0, tranif1

  gate #(3delays) instance_name[range] (list_of_ports);

For tran, rtran

  gate instance_name[range] (list_of_ports);

  pullup (pullup_strength) instance_name[range] (list_of_ports);

  pulldown (pulldown_strength) instance_name[range] (list_of_ports);

Description

Gate or switch declaration begins with a keyword that determines the type of a gate or switch followed by a strength and delay declaration, name of the instance, range, and a list of connections to the gate or switch ports. The strength and the delay declarations are optional. The name of an instance and a range are also optional. Instantiations of individual gate types are not identical.

and, nand, or, nor, xor, xnor gates

The instantiation of these logic gates (Example 1) can contain zero, one, or two delays. The strength declaration should contain two specified strengths - strength1 and strength0 (seeStrengths for more explanations).

These gates have one output and one or more inputs. The first port on the port list is output port.

and 0 1 x z 0 0 0 0 0 1 0 1 x x x 0 x x x z 0 x x x

or 0 1 x z 0 0 1 x x 1 1 1 1 1 x x 1 x x z x 1 x x

xor 0 1 x z 0 0 1 x x 1 1 0 x x x x x x x z x x x x

 

nand 0 1 x z 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x

nor 0 1 x z 0 1 0 x x 1 0 0 0 0 x x 0 x x z x 0 x x

xnor 0 1 x z 0 1 0 x x 1 0 1 x x x x x x x z x x x x

Table 1 Truth tables for logic gates

buf and not gates

The instantiation of these logic gates (Example 2) can contain zero, one, or two delays. The strength declaration should contain two specified strengths - strength1 and strength0 (see Strengths for more explanations).

These gates have one input and one or more outputs. The last port on the port list is an input port.

buf input output 0 0 1 1 x x z x

not input output 0 1 1 0 x x z x

Table 2 Truth tables for logic gates

bufif1, bufif0, notif1, notif0 gates

The instantiation of these tri-state gates (Example 3) can contain zero, one, two, or three delays. The strength declaration should contain two specified strengths - strength1 andstrength0 (see Strengths for more explanations).

These gates have three ports: the first is an output port, the second is a data port, and the third is a control port. The control port is used to set gates in high-impedance state.

bufif0 control input   0 1 x z data input 0 0 z L L 1 1 z H H x x z x x z x z x x

bufif1 control input   0 1 x z data input 0 z 0 L L 1 z 1 H H x z x x x z z x x x

Table 3 Truth table for tri-state logic gates

The L and H symbols have a special meaning. The L symbol means that the output has 0 or z value. The H symbol means that the output has 1 or z value. Any transition to H or L is treated as a transition to x.

nmos, pmos, rnmos, rpmos, cmos, and rcmos switches

The nmos switch is used to model N-type MOS (Metal-Oxide Semiconductor) transistor and the pmos switch is used to model P-type MOS (Metal-Oxide Semiconductor) transistor. The rnmos switch is used to model resistive nmos transistor and the rpmos switch is used to model resistive pmos transistor. The cmos switch should be treated as combination of a pmos switch and an nmos switch, which have common data input and data output. The rcmos switch should be treated as combination of an rpmos switch and an rnmos switch, which have common data input and data output.

The instantiation of these MOS switches (Example 4) can contain zero, one, two, or three delays.

The strength declaration is illegal. The nmos, pmos and cmos switches reduce supply strength of the signals to strong strength. Signals with others strengths are passed from input to output without a strength reduction. The rnmos, rpmos and rcmos switches reduce supply and strong strength of signals to pull strength. The pull strength of signals is reduced toweak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.

The nmos, pmos, rnmos, rpmos switches have three ports: the first is an output port, the second is a data port, and the third is a control port.

The cmos and rcmos switches have four ports: the first is an output port, the second is a data port, the third is a n-control port, and the fourth a is p-control port.

pmos control input rpmos 0 1 x z data input 0 0 z L L 1 1 z H H x x z x x z z z z z

nmos control input rmos 0 1 x z data input 0 z 0 L L 1 z 1 H H x z x x x z z z z z

 

cmos

N control

rmos

0

1

x

z

P control

0

1

x

z

0

1

x

z

0

1

x

z

0

1

x

z

Data

0

0

z

L

L

0

0

0

0

0

L

L

L

0

L

L

L

1

1

z

H

H

1

1

1

1

1

H

H

H

1

H

H

H

x

x

z

x

x

x

x

x

x

x

x

x

x

x

x

x

x

z

z

z

z

z

z

z

z

z

z

z

z

z

z

z

z

z

Table 4 Truth tables for MOS switches

Symbols L and H have a special meaning. The symbol L means that the output has 0 or z value. The symbol H means that the output has 1 or z value. Any transition to H or L is treated as a transition to x.

rtranif0, rtranif1, tranif0 and tranif1 switches

The instantiation of these bi-directional pass switches (Example 5) can contain zero, one, two, or three delays.

The strength declaration is illegal. The tranif0 and tranif1 switches reduce supply strength of signals to strong. Signals with others strengths are passed from input to output without strength reduction. The rtranif0 and rtranif1 switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weakstrength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.

The rtranif0, rtranif1, tranif0 and tranif1 switches have three ports: two bidirectional data ports and one control port (third position on port list).

tran and rtran switches

The instance of these bidirectional switches cannot contain delay and strength declaration.

The tran switches reduce supply strength of signals to strong strength. Signals with others strengths are passed from input to output without strength reduction. The rtran switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The mediumstrength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.

The tran and rtran switches have two bidirectional data ports.

pullup and pulldown sources

The instantiation pullup and pulldown sources cannot contain delay declaration. The pullup can contain only strength1 specification (the strength0 declaration is optional). The pulldown can contain only strength0 specification (the strength1 declaration is optional).

The pullup source places a logic value 1 on connected signals. The pulldown source places a logic value 0 on connected signals.

Examples

Example 1

and (strong1, weak0) (y, i1, i2, i3);

This is a three-input and gate instance with strengths specified. There is no instance name and no delays declaration.

nand #(1,2) gate1 (y, i1, i2);

This is a two-input nand gate instance with two delays specified. The instance name is gate1 and there is no strength specified.

or #1 b[1:0] (y, i1, i2, i3, i4);

This is two instances of two four-input or gates with one delay specified. Names for the instances are b[1] and b[0]. There are no strengths specified.

Example 2

buf (o1, o2, o3, o4, i);

This is the instance of buf gate, which has four outputs and one input.

Example 3

bufif0 (weak1, pull0) #(4,5,3) (data_out, data_in, ctrl);

The bufif0 gate instance with strength and delays is specified. There is no instance name, which is optional.

Example 4

pmos (data_out, data_in, ctrl);
cmos (data_out, data_in, n_ctrl, p_ctrl);

The pmos and cmos switches are instantiated with no delays, strength and instance name declarations.

Important Notes

· Instantiations of gates and switches are different for individual types.

Block Statements

Formal Definition

The block statements provide a means of grouping two or more statements in the block.

Simplified Syntax

begin : name

  statement;

  ...

end

fork : name

  statement;

  ...

join

Description

The Verilog HDL contains two types of blocks:

· Sequential (begin-end blocks).

· Parallel (fork-join blocks).

These blocks can be used if more than one statement should be executed.

All statements within sequential blocks (Example 1) are executed in the order in which they are given. If a timing control statement appears within a block, then the next statement will be executed after that delay.

All statements within parallel blocks (Example 2) are executed at the same time. This means that the execution of the next statement will not be delayed even if the previous statement contains a timing control statement.

Examples

Example 1

begin
  a = 1;
  #10 a = 0;
  #5 a = 4;
end

During the simulation, this block will be executed in 15 time units. At time 0, the 'a' variable will be 1, at time 10 the 'a' variable will be 0, and at time 15 (#10 + #5) the 'a' variable will be 4.

Example 2

fork
  a = 1;
  #10 a = 0;
  #5 a = 4;
join

During the simulation this block will be executed in 10 time units. At time 0 the 'a' variable will be 1, at time 5 the 'a' variable will be 4, and at time 10 the 'a' variable will be 0.

Example 3

fork
  a = 1;
  @(b);
  a = 0;
join

During the simulation when this block is executed 'a' becomes 1 and when a change occurs on 'b', then 'a' changes to 0. Flow of the procedural block is suspended when the @(b) statement is reached awaiting a change in value of 'b' before procedure block activities resume.

Important Notes

· In parallel blocks all statements are executed at the same time, so there must not be any mutual dependent assignments.

Bit-select

Formal Definition

The bit-select provides an access to individual bits of vectors.

Simplified Syntax

vector_identifier[expression];

Description

The bit-select can be used to access individual bits of vector net or register data types. The bits can be addressed by using an expression. If the expression value is out of bounds or it returns z or x values, then the value returned by the reference is x. If one or more bits of the address returned by the expression have an x or z value, then the address expression is x.

The bit-select can be applied to any net vectors, regs, integers, and time register data types. The bit-selection of a register declared as real or realtime is illegal.

Examples

Example 1

reg [3:0] vect;
vect = 4'b0001;

If the value of address expression is 0 then returned value is 1 (vect[0] = 1).

If the value of address expression is 3 then returned value is 0 (vect[3] = 0).

If the value of address expression is 4 then returned value is x (vect[4] = x).

If the value of address expression is x or z then returned value is x (vect[1'bx] = x).

Example 2

reg [0:3] vect;
vect = 4'b0001;

If the value of address expression is 3 then returned value is 1 (vect[3] = 1).

If the value of address expression is 0 then returned value is 0 (vect[0] = 0).

Example 3

reg [7:0] vect;
vect = 4;

Fills vect with the pattern 00000100 (MSB is bit 7, LSB is bit 0).

Important Notes

• If the address expression is out of bounds or it returns an x or z value, then the returned value is x.
• The bit-select of real or realtime registers is illegal.