Parameters

Formal Definition

Parameters are constants typically used to specify the width of variables and time delays.

Simplified Syntax

parameter identifier = constant_expression ,

identifier = constant_expression ;

defparam hierarchical_path = constant_expression ;

Description

In Verilog HDL, parameters are constants and do not belong to any other data type such as net or register data types.

A constant expression refers to a constant number or a previously defined parameter (see Example 1). You are not allowed to modify parameter values at runtime, but you can modify a parameter value using the defparam statement. The defparam statement can modify parameters only at the time of compilation. Parameter values can also be modified using #delay specification with module instantiation.

In Verilog there are two ways to override a module parameter value during a module instantiation. The first method is by using the defparam keyword and the second method is called module instance parameter value assignment.

After the defparam keyword, the hierarchical path to the parameter is specified along with the new value of the parameter. In this case, the new value should be a constant expression (see Example 2). If the right-hand side expression references any parameters it should be declared within the module where defparam is invoked (see Example 3).

The module instance parameter value assignment method looks like an assignment of delay to gate instance (see Example 4). This method overrides parameters inside instantiated modules, in the order, that they appear in the module. Using this format, parameters cannot be skipped.

Constant expressions can contain previously declared parameters. When changes are detected on the previously declared parameters, all parameters that depend on this value are automatically updated (see Example 5).

Examples

Example 1

parameter lsb = 7 ;
parameter size = 8 ,
word = 32 ;
parameter number = 3.92,
frequency = 100 ;
parameter clk_cycle = frequency / 2 ;

Example 2

module my_module (Clk, D, Q) ;
parameter width = 2,
delay = 10 ;
input [width - 1 : 0] D ;
input Clk ;
output [width : 0] Q ;
assign #delay Q = D;
endmodule

Example 3

module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module inst_1(Clk, D, Q) ;
endmodule
module override ;
defparam top.inst_1.width = 7 ;
endmodule

Example 4

module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module #(7, 25) inst_1(Clk, D, Q) ;
endmodule

Example 5

parameter foo = 4;
parameter data = foo / 10 ;

When 'foo' changes, 'data' is automatically updated.

Important Notes

• Parameters are constants.
• If you are using the defparam statement, remember that you have to specify a hierarchical path to your parameter.
• You cannot skip over a parameter in a module instance parameter value assignment. If you need do this, use the initial value for parameter that is not to be overwritten.
• When one parameter depends on the other, remember that if you change the first one, the second will automatically be updated.

Net Data Types

Formal Definition

Nets are data types that can be used to model physical connections.

Simplified Syntax

Net declaration:

wire range delays list_of_identifiers;

wand range delays list_of_identifiers;

wor range delays list_of_identifiers;

tri range delays list_of_identifiers;

triand range delays list_of_identifiers;

trior range delays list_of_identifiers;

tri0 range delays list_of_identifiers;

tri1 range delays list_of_identifiers;

supply0 range delays list_of_identifiers;

supply1 range delays list_of_identifiers;

trireg strength range delays list_of_identifiers;

Net declaration assignment:

wire strength range delays list_of_identifiers = expression;

wand strength range delays list_of_identifiers = expression;

wor strength range delays list_of_identifiers = expression;

tri strength range delays list_of_identifiers = expression;

triand strength range delays list_of_identifiers = expression;

trior strength range delays list_of_identifiers = expression;

tri0 strength range delays list_of_identifiers = expression;

tri1 strength range delays list_of_identifiers = expression;

supply0 strength range delays list_of_identifiers = expression;

supply1 strength range delays list_of_identifiers = expression;

trireg strength range delays list_of_identifiers = expression;

Description

Net data types are used to model physical connections. They do not store values (there is only one exception - trireg, which stores a previously assigned value). The net data types have the value of their drivers. If a net variable has no driver, then it has a high-impedance value (z).

Nets can be declared in a net declaration statement (Example 1) or in a net declaration assignment (Example 2).

Net declarations can contain strength declarations, which specifies the strength of the logic values driven by the net (see Strengths for more details). The range declaration is used to specify multi-bit nets (vectors). The delays are used to specify propagation delays through the nets. The strength, delay and range declarations are optional.

Wire and tri nets.

Both wire net and tri net are identical. Two different names are used for more readability. Preferably wire nets may be used if a net has only one driver. If a net has more than one driver, then tri net may be used instead.

	0	1	x	z
0	0	x	x	0
1	x	1	x	1
x	x	x	x	x
z	0	1	x	z

Table 8: Truth table for wire and tri nets

This table applies only to wire and tri nets driven by multiple drivers that have no strength declaration or their strengths are equal.

Wand and triand nets.

These net types are wired and nets. It means that if one of their drivers is 0 then the result value will also be 0.

	0	1	x	z
0	0	0	0	0
1	0	1	x	1
x	0	x	x	x
z	0	1	x	z

Table 9: Truth table for wand and triand nets

This table applies only to wand and triand nets driven by multiple drivers that have no strength declaration, or their strengths are equal.

Wor and trior nets.

These net types are wired or nets. It means that if one of their drivers has a value of 1, then the result value will also be 1.

	0	1	x	z
0	0	1	x	0
1	1	1	1	1
x	x	1	x	x
z	0	1	x	z

Table 10: Truth table for wor and trior nets

This table applies only to wor and trior nets driven by multiple drivers that have no strength declaration, or their strengths are equal.

Tri0 and tri1 nets.

These nets are used to model resistive pulldown and pullup devices. If a tri0 net has no driver its value is 0. If a tri1 net has no driver, then its value is 1. These values have pull strength.

	0	1	x	z
0	0	x	x	0
1	x	1	x	1
x	x	x	x	x
z	0	1	x	0

Table 11: Truth table for tri0 net

	0	1	x	z
0	0	x	x	0
1	x	1	x	1
x	x	x	x	x
z	0	1	x	1

Table 12: Truth table for tri1 nets

Supply0 and supply1 nets.

These nets are used to model power supplies in the circuit. They should have supply strength.

Trireg nets.

The trireg nets are used to model net capacity. If the trireg net driver has 0, 1, or x value, then it becomes a trireg net value and its strength can be one of the drive strengths, depending on the driver strength. If the driver has a z value, then the trireg net keeps the previously driven value and the strength can be one of the charge strengths, depending on the strength specified during net declaration.

Examples

Example 1

wire [7:0] a;
tri tristate_buffer;
wand #5 sig_1;
trireg (small) t;

The 'a' variable is a 8-bit wire net.

The 'tristate_buffer' is 1-bit tri net type variable.

The 'sig_1' variable is 1-bit wand net type variable, which propagates driven value to its output in 5 time units.

The 't' variable is trireg net variable with small charge strength.

Example 2

reg a;
wire [3:0] b;
wor (strong1, weak0) wired_or = a;
trior (pull1, weak0) [3:0] #(5:3:4) vect = b;

The 'wired_or' variable is a 1-bit wor net type variable that has specified strengths (strong1 when its value is 1 and weak0 when its value is 0).

The 'vect' variable is a 4-bit trior net type variable that has pull and weak strengths and 3 delay parameters.

Important Notes

• Nets cannot be used as left-hand value of procedural assignments.
• If the trireg net is not driven, then it has charge strength. Otherwise it has the strength of its driver.

Operators

Formal Definition

Operators provide a means to construct expressions.

Simplified Syntax

Arithmetic: + - * /

Modulus: %

Relational: < <= > >=

Logical: ! && ||

Logical equality: == !=

Case equality: === !==

Bit-wise: ~ & | ^ ~^ ^~

Reduction: & ~& | ~| ^ ~^ ^~

Shift: << >>

Conditional: ?:

Event or: or

Concatenations: {} {{}}

Description

Verilog HDL operators can be divided into several groups.

Operator	Description
+ - ! ~	Unary
* / %	Arithmetic
+ - (binary)	Binary
<< >>	Shift
< <= > =>	Relational
== != === !==	Equality
& ~&	and nand
^ ~^ ^~	xor xnor
| ~|	or nor
&&	Logical and
||	Logical or
?:	Conditional operator

Table 13: Operator's priority

Arithmetic operators

The arithmetic operators can be used with all data types.

Operator	Description
a + b	a plus b
a - b	a minus b
a * b	a multiply by b
a / b	a divide by b
a % b	a modulo b

Table 14: Arithmetic operators

The modulus operator is not allowed for real data type variables. For the modulus operator, the result takes the sign of the first operand. Examples of using these operators are shown in Example 1.

Relational operators

The relational operators are used to compare expressions. The value returned by the relational operators is 0 if the expression evaluates to false and 1 if expression evaluates to true.

Operator	Description
a < b	a less than b
a > b	a greater than b
a <= b	a less than or equal to b
a => b	a greater than or equal to b

Table 15: Relational operators

Examples of using the relational operators are shown in Example 2.

Equality operators

The equality operators are used to compare expressions. If a comparison fails, then the result will be 0, otherwise it will be 1.

If both operands of logical equality (==) or logical inequality (!=) contain unknown (x) or a high-impedance (z) value, then the result of comparison will be unknown (x). Otherwise it will be true or false.

If operands of case equality (===) or case inequality (!==) contain unknown (x) or a high-impedance (z) value, then the result will be calculated bit by bit.

Examples of using the equality operators are shown in Example 3.

Logical operators

The logical operators are used to connect expressions.

Operator	Description
a && b	a and b
a || b	a or b
!a	not a

Table 16: Logical operators

The result for these operators is 0 (when false), 1 (when true), and unknown (x - when ambiguous). The negation operator (!) turns a nonzero or true value of the operand into 0, zero or false value into 1, and ambiguous value of operator results in x (unknown value).

Examples of using the logical operators are shown in Example 4.

Bit-wise operators

The bit-wise operators calculate each bit of results by evaluating the logical expression on a pair of corresponding operand bits.

&	0	1	x	z
0	0	0	0	0
1	0	1	x	x
x	0	x	x	x
z	0	x	x	x

Table 17: Bit-wise and operator

|	0	1	x	z
0	0	1	x	x
1	1	1	1	1
x	x	1	x	x
z	x	1	x	x

Table 18: Bit-wise or operator

^	0	1	x	z
0	0	1	x	x
1	1	0	x	x
x	x	x	x	x
z	x	x	x	x

Table 19: Bit-wise exclusive or operator

~^ ^~	0	1	x	z
0	1	0	x	x
1	0	1	x	x
x	x	x	x	x
z	x	x	x	x

Table 20: Bit-wise exclusive nor operator

~	Result
0	1
1	0
x	X
z	X

Table 21: Bit-wise negation operator

Examples of using the bit-wise operators are shown in Example 5.

Reduction operators

The reduction operator produces a 1-bit result. This result is calculated by recursively applying bit-wise operation on all bits of the operand. At each step of this recursive calculation the logical bit-wise operation is performed on the result of a previous operation and on the next bit of the operand. The operation is repeated for all bits of the operand.

Examples of using the reduction operators are in shown Example 6.

Shift operators

The shift operators perform left and right shifts on their left operand by the number of positions specified by their right operand. All vacated bits are filled with zeroes. If the expression that specifies the number of bits to shift (right operand) has unknown (x) or high-impedance (z) value, then result will be unknown.

Examples of using the shift operators are in shown Example 7.

Conditional operator

The conditional operator is described in the Conditional operator section.

Concatenations

Concatenations are described in the Concatenations section.

Event or operator

The event or operator is described in the section on Procedural timing controls.

Examples

Example 1

reg [3:0] a, b;
a = 4;
b = 3;
a + b = 7
a - b = 1
a * b = 12
a / b = 1
a % b = 1
5 % 2 = 1
5 % -2 = 1
-5 % 2 = -1
-5 % -2 = -1

Example 2

reg [3:0] a, b;
a = 4'b1100;
b = 4'b0110;
a < b // false - 0
a > 8 // true - 1
a <= b // false - 0
a >= 10 // true - 1
a < 4'b1zzz // unknown - x
a < 4'b1x01 // unknown - x

Example 3

reg [3:0] a, b;
a = 4'b1100;
b = 4'b101x;
a == 4'b1100 // true - 1
a != 4'b1100 // false - 0
a == 4'b1z10 // false - 0
a != 4'b100x // true - 1
b == 4'b101x // unknown - x
b != 4'b101x // unknown - x
b === 4'b101x // true - 1
b !== 4'b101x // false - 0

Example 4

reg [3:0] a, b;
a = 4'b1100;
b = 4'b0000;
!a // 0 - false
!b // 1 - true
a && b // 0 - false
a || b // 1 - true

Example 5

reg [7:0] a, b;
a = 8'b1010xzxz;
b = 8'b10010011;
a & b = 8'b100000xx;
a | b = 8'b1011xx11;
a ^ b = 8'b0011xxxx;
a ~^ b = 8'b1100xxxx;
~ a = 8'b0101xxxx;

Example 6

value	&	~&	|	~|	^	~^	^~
4'b0000	0	1	0	1	0	1	1
4'b0001	0	1	1	0	1	0	0
4'b0011	0	1	1	0	0	1	1
4'b0111	0	1	1	0	1	0	0
4'b1111	1	0	1	0	0	1	1
4'b01xx	0	1	1	0	x	x	x
4'b01z0	0	1	1	0	x	x	x

Table 22: Reduction operators

Example 7

reg [3:0] a;
a = 4'b1111;
a << 3 = 4'b1000
a >> 3 = 4'b0001
a << 1'bz = 4'bxxxx
a >> 1'bx = 4'bxxxx

Important Notes

• Some of the operators cannot be used with reals.

Module Instantiation

Formal Definition

Module instantiation provides a means of nesting modules descriptions.

Simplified Syntax

module_name [parameter_value_assignment] module_instance ;

Description

Modules can be instantiated from within other modules. When a module is instantiated, connections to the ports of the module must be specified. There are two ways to make port connections. One is connection by name, in which variables connected to each of module inputs or outputs are specified in a set of parenthesis following the name of the ports. In this method order of connections is not significant. See Example 1.

The second method is called ordered connection. In this method the order of the ports must match the order appearing in the instantiated module. See Example 2. When ports are connected by name it is illegal to leave any ports unconnected. This may occur when ports are connected by order. See Example 3.

What happens if you leave a port unconnected depends on the type of the port. If you are connecting net type ports, unconnected bits are driven with high impedance. In other cases, bits are driven with unknown values.

Module instantiations can create an array of instances. To create theses instances, range specifications have to be declared after the module name. The array of instances can save you time in writing code and provide a way to enrich your readability, see Example 4

Examples

Example 1

module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
  dff inst_1 (.d(data), .q(net_1), .clk(clock));
  dff inst_2 (.clk(clock), .d(net_1), .q(q_out));

endmodule

In the top module there are two instantiations of the 'dff' module. In both cases port connections are done by name, so the port order is insignificant. The first port is input port 'd', the second is output 'q' and the last is the clock in the 'inst_1'. In the dff module the order of ports is different than either of the two instantiations.

Example 2

module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
  dff inst_1 (clock, data, net_1);
  dff inst_2 (clock, net_1, q_out);
endmodule

Example 3

dff inst_1 (clock, , net_1);

Second port is unconnected and has the value Z because it is of the net type.

Example 4

module my_module (a, b, c);
input a, b;
output c;
  assign c = a & b ;
endmodule
module top (a, b, c) ;
input [3:0] a, b;
output [3:0] c;
  my_module inst [3:0] (a, b, c);
endmodule

Important Notes

· If ports are connected by name it is illegal to leave any ports unconnected.

Module Path Polarity

Formal Definition

Module path polarity describes when a signal is inverted or not driving propagation between the source and the destination .

Simplified Syntax

+=> positive simple module path polarity

-=> negative simple module path polarity

+*> positive multiple module path polarity

-*> negative multiple module path polarity

Description

The polarity of the module is a description of what happens when a signal is propagated from the source to the destination. There are three possible polarities of the module.

· Unknown polarity

· Positive polarity

· Negative polarity

Positive polarity is specified by the + prefix. When positive polarity is specified, simple rules apply: a rise at the source causes a rise transition at the destination and a fall transition at the source causes the fall transition at the destination. (Example 1)

Negative polarity is specified by the - prefix. When negative polarity is specified, the rules applied are similar to those from positive polarity. However, a rise transition at the source causes fall transition at the destination, and a fall transition at the source causes a rise transition at the destination. (Example 2)

When no prefix is specified with => or *> operators, it means that unknown polarity is to be used by default. In this case a rise transition at the source may cause a rise, a fall, or no transition at the destination. The same rule applies for the fall transition. (Example 3)

Examples

Example 1

(DataIn +=> DataOut) = DataIn_to_DataOut ;
(DataIn +*> DataOut) = DataIn_to_DataOut ;

Positive polarity.

Example 2

(DataIn -=> DataOut) = DataIn_to_DataOut ;
(DataIn -*> DataOut) = DataIn_to_DataOut ;

Negative polarity.

Example 3

(DataIn => DataOut) = DataIn_to_DataOut ;
(DataIn *> DataOut) = DataIn_to_DataOut ;

Default unknown polarity.

Important Notes

· By default, unknown polarity is specified.

· Module path polarity is used by a timing analysis tool and is ignored by the simulator.

Module Path Declaration

Formal Definition

Module path declaration is used to describe how data can propagate through a module.

Simplified Syntax

Simple module path ;

Edge sensitive path ;

State dependent path ;

Description

Let's take a look at this model:

The problem is to define delays between input and output (Y and A for example). The solution is to declare a path and specify a delay. There are three ways to do this:

· Declare a simple module path

· Edge a sensitive path

· State a dependent path.

The idea is to define the delay from the source to the destination. In this method each path can have a specific delay difference. For example, the path between Y and A can be different than Y and B. Generally, if a delay is specified, we know when the response occurs on the output if the input changes.

Examples of module path declarations are also described in chapters: Edge sensitive path, and State dependent path.

Examples

Simple module path example:

(A => Q) = 10;
(B => Q) = (12);
(C, D *> Q) = 18;

The symbols *> and => each represent a different kind of connection between the module path source and the module path destination. The operator *> establishes a full connection between source and destination. The operator => establishes a parallel connection between source and destination. Refer to the Language Reference Manual for a description of full connection and parallel connection paths.

Important Notes

· Module paths cannot be declared outside of a module.

· Only the net type of a port can be used as a source. Input and inout directions are allowed.

· Both registers and net types can be used as path destinations. Input and inout directions are allowed.

· A destination cannot have more than one driver.

Module Declaration

Formal Definition

A module is comprised of the interface and the design behavior.

Simplified Syntax

module | macromodule identifier (port_list) ;

  ports_declaration ;

  module_body ;

endmodule

Description

All module declarations must begin with the module (or macromodule) keyword and end with the endmodule keyword. After the module declaration, an identifier is required. A ports list is an option. After that, ports declaration is given with declarations of the direction of ports and the optionally type. The body of module can be any of the following:

· Any declaration including parameter, function, task, event or any variable declaration.

· Continuous assignment.

· Gate, UDP or module instantiation.

· Specify block.

· Initial block

· Always block.

If there is no instantiation inside the module, it will be treated as a top-level module

Examples

Example 1

module module_1(a, b, c) ;
parameter size = 3 ;
input [size : 0] a, b ;
output [size : 0] c;
assign c = a & b;
endmodule

Module declaration with a parameter declaration.

Important Notes

· If there are two or more modules without instantiation inside the modules, then they are treated as the top-level. This means that you can have several of top-level modules.