Procedure

Formal Definition

A procedure is a subprogram that defines algorithm for computing values or exhibiting behavior. Procedure call is a statement.

Simplified Syntax

procedure procedure_name ( formal_parameter_list )

procedure procedure_name ( formal_parameter_list ) is

  procedure_declarations

  begin

    sequential statements

  end procedure procedure_name;

Description

The procedure is a form of subprograms. It contains local declarations and a sequence of statements. Procedure can be called in any place of the architecture. The procedure definition consists of two parts:

· the procedure declaration, which contains the procedure name and the parameter list required when the procedure is called;

· the procedure body, which consists of the local declarations and statements required to execute the procedure.

PROCEDURE DECLARATION

The procedure declaration consists of the procedure name and the formal parameter list.

In the procedure specification, the identifier and optional formal parameter list follow the reserved word procedure (Example 1).

Objects classes constants, variables, signals, and files can be used as formal parameters. The class of each parameter is specified by the appropriate reserved word, unless the default class can be assumed (see below). In case of constants, variables and signals, the parameter mode determines the direction of the information flow and it decides which formal parameters can be read or written inside the procedure. Parameters of the file type have no mode assigned.

There are three modes available: in, out, and inout. When in mode is declared and object class is not defined, then by default it is assumed that the object is a constant. In case ofinout and out modes, the default class is variable. When a procedure is called, formal parameters are substituted by actual parameters. If a formal parameter is a constant, then actual parameter must be an expression. In case of formal parameters such as signal, variable and file, the actual parameters must be objects of the same class. Example 2 presents several procedure declarations with parameters of different classes and modes.

A procedure can be declared also without any parameters.

PROCEDURE BODY

Procedure body defines the procedure's algorithm composed of sequential statements. When the procedure is called it starts executing the sequence of statements declared inside the procedure body.

The procedure body consists of the subprogram declarative part After the reserved word is and the subprogram statement part placed between the reserved words begin and end. The key word procedure and the procedure name may optionally follow the end reserved word.

Declarations of a procedure are local to this declaration and can declare subprogram declarations, subprogram bodies, types, subtypes, constants, variables, files, aliases, attribute declarations, attribute specifications, use clauses, group templates and group declarations (Example 3).

A procedure can contain any sequential statements (including wait statements). A wait statement, however, cannot be used in procedures which are called from a process with a sensitivity list or from within a function. Examples 4 and 5 present two sequential statements specifications.

PROCEDURE CALL

A procedure call is a sequential or concurrent statement, depending on where it is used. A sequential procedure call is executed whenever control reaches it, while a concurrent procedure call is activated whenever any of its parameters of in or inout mode changes its value.

All actual parameters in a procedure call must be of the same type as formal parameters they substitute.

OVERLOADED PROCEDURES

The overloaded procedures are procedures with the same name but with different number or different types of formal parameters. The actual parameters decide which overloaded procedure will be called (Example 6).

Examples

Example 1

procedure Procedure_1 (variable X, Y: inout Real);

The above procedure declaration has two formal parameters: bi-directional variables X and Y of the real type.

Example 2

procedure Proc_1 (constant In1: in Integer; variable O1: out Integer);
procedure Proc_2 (signal Sig: inout Bit);

Procedure Proc_1 has two formal parameters: the first one is a constant and it is of mode in and of the integer type, the second one is an output variable of the integer type.

Procedure Proc_2 has only one parameter, which is a bi-directional signal of the type BIT.

Example 3

procedure Proc_3 (X,Y : inout Integer) is
  type Word_16 is range 0 to 65536;
  subtype Byte is Word_16 range 0 to 255;
  variable Vb1,Vb2,Vb3 : Real;
  constant Pi : Real :=3.14;
  procedure Compute (variable V1, V2: Real) is
  begin
    -- subprogram_statement_part
  end procedure Compute;
begin
    -- subprogram_statement_part
end procedure Proc_3;

The example above present different declarations which may appear in the declarative part of a procedure.

Example 4

procedure Transcoder_1 (variable Value: inout bit_vector (0 to 7)) is
begin
  case Value is
    when "00000000" => Value:="01010101";
    when "01010101" => Value:="00000000";
    when others => Value:="11111111";
  end case;
end procedure Transcoder_1;

The procedure Transcoder_1 transforms the value of a single variable, which is therefore a bi-directional parameter.

Example 5

procedure Comp_3(In1,R:in real; Step :in integer; W1,W2:out real) is
variable counter: Integer;
begin
  W1 := 1.43 * In1;
  W2 := 1.0;
  L1: for counter in 1 to Step loop
    W2 := W2 * W1;
    exit L1 when W2 > R;
  end loop L1;
  assert ( W2 < R )
    report "Out of range"
      severity Error;
end procedure Comp_3;

The Comp_3 procedure calculates two variables of mode out: W1 and W2, both of the REAL type. The parameters of mode in: In1 and R constants are of real type and Step of the integer type. The W2 variable is calculated inside the loop statement. When the value of W2 variable is greater than R, the execution of the loop statement is terminated and the error report appears.

Example 6

procedure Calculate (W1,W2: in Real; signal Out1:inout Integer);
procedure Calculate (W1,W2: in Integer; signal Out1: inout Real);
-- calling of overloaded procedures:
Calculate(23.76, 1.632, Sign1);
Calculate(23, 826, Sign2);

The procedure Calculate is an overloaded procedure as the parameters can be of different types. Only when the procedure is called the simulator determines which version of the procedure should be used, depending on the actual parameters.

Important Notes

· The Procedure declaration is optional - procedure body can exist without it. If, however, a procedure declaration is used, then a procedure body must accompany it.

· Subprograms (procedures and functions) can be nested.

· Subprograms can be called recursively.

· Synthesis tools usually support procedures as long as they do not contain the wait statements.

Process Statement

Formal Definition

A process statement defines an independent sequential process representing the behavior of some portion of the design.

Simplified Syntax

[process_label:] process [ ( sensitivity_list ) ] [ is ]

    process_declarations

    begin

     sequential_statements

    end process [ process_label ] ;

Description

The process statement represents the behavior of some portion of the design. It consists of the sequential statements whose execution is made in order defined by the user.

Each process can be assigned an optional label.

The process declarative part defines local items for the process and may contain declarations of: subprograms, types, subtypes, constants, variables, files, aliases, attributes, use clauses and group declarations. It is not allowed to declare signals or shared variables inside processes.

The statements, which describe the behavior in a process, are executed sequentially, in the order in which the designer specifies them. The execution of statements, however, does not terminate with the last statement in the process, but is repeated in an infinite loop. The loop can be suspended and resumed with wait statements. When the next statement to be executed is a wait statement, the process suspends its execution until a condition supporting the wait statement is met. See respective topics for details.

A process declaration may contain optional sensitivity list. The list contains identifiers of signals to which the process is sensitive. A change of a value of any of those signals causes the suspended process to resume. A sensitivity list is a full equivalent of a wait on sensitivity_list statement at the end of the process. It is not allowed, however, to use wait statements and sensitivity list in the same process. In addition, if a process with a sensitivity list calls a procedure, then the procedure cannot contain any wait statements.

Examples

Example 1

entity D_FF is
port (D,CLK : in BIT;
      Q : out BIT := '0';
      NQ : out BIT := '1' );
end entity D_FF;
architecture A_RS_FF of D_FF is
begin
  BIN_P_RS_FF: process (CLK)
  begin
    if CLK = '1' and CLK'Event then
      Q <= D;
      NQ <= not D;
    end if;
  end process;
end architecture A_RS_FF;

The flip-flop has two input ports: D, CLK and two output ports: Q and NQ. The value of the input signal D is assigned to the output Q when the value of the CLK changes from '0' to '1'. The change of the signal value initiates the process BIN_P_RS_FF, because the signal CLK is on the sensitivity list of this process. The change of the CLK value from the logical zero to the logical one is sensed by the use of the if statement.

The first part of if statement takes place when the actual value of the signal CLK is checked. The second part confirms that the signal CLK really changes its value (attribute 'Event is responsible for that). In the case when the logical value of this condition is TRUE, then the two assignment signal statement are executed.

Important Notes

• Sensitivity list and explicit wait statements may not be specified in the same process.

Range

Formal Definition

A specified subset of values of a scalar type.

Simplified Syntax

range left_bound to right_bound

range left_bound downto right_bound

range <>

Description

The range specifies a subset of values of a scalar type. This range can be null range if the set contains no values. A range can be either ascending or descending.

A range is called ascending if it is specified with the keyword to as the direction and the left bound value is smaller than the right bound (otherwise the range is null). A range isdescending if the range is specified with the keyword downto as the direction and the left bound is greater than the right bound (otherwise the range is null).

A value X belongs to a range if this range is not a null range and the following relation holds:

lower bound of the range <= X <= upper bound of the range

A range can be undefined. Such a range is used in declaration of unconstrained arrays and is illustrated in example 2.

Examples

Example 1

1 to 100
7 downto 0
5 to 0

The first range is an ascending range of the values of integer type. The second range is also of integer type, but descending. Finally, the third range is null.

Example 2

type Mem is array (NATURAL range <>) of Bit_Vector(7 downto 0);

The type Mem is declared as an unconstrained array of bytes (8-bit wide vectors of bits). Note the way an undefined range is declared.

Important Notes

· Ranges do not have to be bounded by discrete numbers. Enumeration types can also be used for ranges (for example 'a' to 'z').

Record Type

Formal Definition

A composite type whose values consist of named elements.

Simplified Syntax

type record_type_name is record

    element_name : element type;

    element_name : element type;

    . . .

    end record record_type_name;

Description

The record type allows declaring composite objects whose elements can be of different types. This is the main difference from arrays, which must have all elements of the same type. All elements are declared with individual names together with subtype indication. If two or more elements are of the same subtype they can be declared together (Example 1). The names of elements in each record must be distinct. The same element name, however, can be used in different records.

The value of an object of type record is a composite value, consisting of the values of its elements. The assignment of a value to an object of the type record can be realized either through an aggregate or through individual assignments to elements (selected names).

Aggregate-based assignment to a record, either positional or named association, can be used (Example 2). If the positional association is used, it is assumed that the elements are listed in the order defined in the record declaration. If the others choice is used, it must represent at least one element. If there are two or more elements assigned by the otherschoice, then all these elements have to be of the same type.

When individual assignment to elements are used then each element id referenced by the record object name followed by a dot and element's name (example 3).

Expression assigned to an element of a record must result in a value of the same type as the element.

Examples

Example 1

type RegName is (AX, BX, CX, DX);
type Operation is record
    Mnemonic : String (1 to 10);
    OpCode : Bit_Vector(3 downto 0);
    Op1, Op2, Res : RegName;
end record;

The record type defined above represents an information from an instruction list of a processor. There are five elements here: mnemonic code (a string), operation code (four bit), two operands and the destination. Note that the last three elements are declared together as they are of the same type.

Example 2

-- type declarations are given in Example 1
variable Instr1, Instr2: Operation;
. . .
Instr1:= ("ADD AX, BX", "0001", AX, BX, AX);
Instr2:= ("ADD AX, BX", "0010", others => BX);

Here, the two assignments to variables of the record type (Operation) are performed with aggregates. Note the way the choice others was used in the second example.

Example 3

-- type declarations are given in Example 1
variable Instr3 : Operation;
. . .
Instr3.Mnemonic := "MUL AX, BX";
Instr3.Op1 := AX;

In this case direct assignments to individual elements of a record object are performed. Note the way an element is referenced: record name, dot, and element name.

Important Notes

· Linear records (i.e. record, where elements are of not of composite type) are generally synthesizable.

· Files are not allowed as elements of records.

Report Statement

Formal Definition

A statement that displays a message.

Simplified Syntax

report string;

report string severity severity_level;

Description

The report statement is very much similar to assertion statement. The main difference is that the message is displayed unconditionally. Its main purpose is to help in the debugging process.

The expression specified in the report clause must be of predefined type STRING, and it is a message that will be reported when the assertion violation occurred.

If the severity clause is present, it must specify an expression of predefined type SEVERITY_LEVEL, which determines the severity level of the assertion violation. The SEVERITY_LEVEL type is specified in the STANDARD package and contains following values: NOTE, WARNING, ERROR, and FAILURE. If the severity clause is omitted in a report statement it is implicitly assumed to be NOTE (unlike in an assertion statement, where the default is ERROR).

Examples

Example 1

while counter <= 100 loop
  if counter > 50
    then report "the counter is over 50";
  end if;
  . . .
end loop;

Whatever happens inside the loop, if the value of counter is greater than 50 it will be reported by the listed message. The severity clause is omitted here because the selected level is the same as the default one (NOTE).

Important Notes

• The report statement was introduced as late as in VHDL 93 and is equivalent to the assert false statement. The latter form was the only acceptable in VHDL 87.

Reserved KeyWord

Definition:

The reserved word is an identifier reserved in the VHDL language for a special purpose.

Description

The reserved words cannot be used as explicitly declared identifiers. The complete list of reserved words is given below:

abs
after
alias
all
and
architecture
array
assert
attribute

begin
block
body
buffer
bus

case
component
configuration
constant

disconnect
downto

else
elsif
end
entity
exit

file
for
function

generate
generic
group
guarded

if
impure
in
inertial
inout
is

label
library
linkage
literal
loop

map
mod

nand
new
next
nor
not
null

of
on
open
or
others
out

package
port
postponed
procedure
process
pure

range
record
register
reject
rem
report
return
rol
ror

select
severity
signal
shared
sla
sll
sra
srl
subtype

then
to
transport
type

unaffected
units
until
use

variable

wait
when
while
with

xnor
xor

Important Notes

· VHDL is case insensitive, therefore there is no difference using either uppercase or lowercase for reserved words.

· If an identifier is placed between leading and trailing backslashes, it becomes an extended identifier and is no longer a reserved word (e.g. \port\ is not a reserved word).

Resolution Function

Formal Definition

A resolution function is a function that defines how the values of multiple sources of a given signal are to be resolved into a single value for that signal.

Simplified Syntax

function function_name (parameters) return type;

function function_name (parameters) return type is

  declarations

  begin

   sequential statements

  end function function_name;

Description

The resolution function allows multiple values to drive a single signal at the same time. This is particularly important for buses, which are connecting multiple sources of data.

The specification of a resolution function is the same as for ordinary functions with one requirement: the resolution function must be pure.

Resolution functions are associated with signals that require resolution by including the name of the resolution function in the declaration of signals or in the declaration of the signal subtype.

Examples

Example 1

TYPE std_ulogic IS ( 'U', -- Uninitialized
                     'X', -- Forcing Unknown
                     '0', -- Forcing 0
                     '1', -- Forcing 1
                     'Z', -- High Impedance
                     'W', -- Weak Unknown
                     'L', -- Weak 0
                     'H', -- Weak 1
                     '-'  -- Don't care
                    );
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
SUBTYPE std_logic IS resolved std_ulogic;
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
--   ---------------------------------------------------------
--   |  U    X    0    1    Z    W    L    H    -        |   |
--   ---------------------------------------------------------
     ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
     ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
     ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
     ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
     ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
     ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
     ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
     ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
     ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )  -- | - |
  );
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
  VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
  IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
    ELSE
      FOR i IN s'RANGE LOOP
        result := resolution_table(result, s(i));
      END LOOP;
  END IF;
  RETURN result;
END resolved;

The example is a part of the Std_Logic_1164 Package specification. The name of the resolution function called Resolved is included into the declaration of the subtype Std_Logic (highlighted by boldface). The resolution function itself is declared at the end of the example.

Important Notes

• Standard types (BIT and BIT_VECTOR) are not resolved and it is not possible to specify multiple-source buses with these types. This is quite restrictive for typical applications, which use buses.

• Because Std_Logic and Std_Logic_Vector are resolved and can handle buses, they became the de facto industrial standard types.