IHS iSuppli: IC inventories hit record levels in Q3

hip inventories reached record highs near the end of 2012, and according to IHS iSuppli, semiconductor revenue will decline in Q1, prompting new concerns about the state of the market.

Overall semiconductor revenue is expected to slide three percent between January and March 2013, on top of a 0.7 percent decline in Q4 2012. What's more, inventory reached record levels in Q3 2012, amounting to 49.3 percent of revenue, more than at any point since Q1 2006. IHS iSuppli believes the uncomfortably high level of inventory points to the failure of key demand drivers to materialize.

The PC market remains slow and hopes of a Windows 8 renaissance have turned into a nightmare. Bellwether Intel saw its revenue drop three percent in Q4, with profit tumbling 27 percent, and the trend is set to continue. AMD is expected to announce its earnings Tuesday afternoon and more gloom is expected across the board. The only bright spot in an otherwise weak market is TSMC, which quickly rebounded after posting the lowest revenues in two years a year ago. TSMC now expects to see huge demand for 28nm products in 2013 and many observers point to a possible deal with Apple.

In addition, TSMC plans to invest $9 billion in capital expenditure in 2013, and it will likely spend even more in 2014, as it moves to ramp up 20nm production. However, Intel's plans to increase capital spending to $13 billion, up $2 billion over 2012 levels, have not been welcomed by analysts and investors. Unlike TSMC, Intel is not investing to increase capacity in the short term, it is making a strategic bet on 450mm wafer technology, which promises to deliver significantly cheaper chips compared to existing 300mm wafers. However, 450mm plants are still years away.

TSMC's apparent success has a lot to do with high demand for Smartphone's and tablets, which are slowly eating into the traditional PC market. Semiconductor shipments for the wireless segment were expected to climb around four percent in 2012 and positive trends were visible in analog, logic and NAND components. However, the mobile boom can't last forever, and we are already hearing talk of "Smartphone fatigue" and "peak Apple".

IHS iSuppli estimates the first quarter of 2013 will see growth in industrial and automotive electronics and other semiconductor markets will eventually overcome the seasonal decline, so a rebound is expected in the second and third quarters.

Semiconductor revenue could grow by four percent in the second, and nine percent in the third quarter. However, the assumptions are based on a wider economic recovery, which is anything but certain at this point. If demand evaporates, semiconductor suppliers could find themselves hit by an oversupply situation, leading to more inventory write-downs throughout the year.

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What Is A 'Clocking Block'?

In Verilog, a module is the unit for any design entity. SystemVerilog extends this to include other design entities such as an interface, a program block and, last but not the least, a clocking block. An interface separates how a design interacts with the rest of the design from the design itself. A program block separates a test benching function from a silicon implementable design. And a clocking block specifies clock signals and the timing and synchronization requirements of various blocks. A clocking block is helpful in separating clocking activities of a design from its data assignments activities and can be used powerfully in test benching.

A clocking block assembles all the signals that are sampled or synchronized by a common clock and define their timing behaviors with respect to the clock. It is defined by a clocking-endclocking keyword pair. Perhaps an example will describe this best.

clocking clock1 @(posedge clk1);
   default input #2ns output #3ns;
   input a1, a2;
   output b1;
endclocking
In the above example,

1. The name of the clocking block is clock1. You can have as many clocking blocks in your environment as you want. Also, there may be multiple clocking blocks for the same clock, inputs or outputs in a single design.
2. The clock associated with this clocking block is clk1. Each clocking block must have at least one clock associated with it.
3. The default keyword defines the default skew for inputs (2 ns) and output (3 ns).
4. The input and output keywords define the input and output signals associated with the clock and the skew defined earlier.
5. One thing to note here is that input or output declarations inside a clocking module does not specify the data width.

A clocking block is both a declaration and an instance of that declaration and can only occur within a module, interface or program block (in the same scope as an always block). Variables inside a clocking block can be accessed specifying the full pathname. For instance, if the full pathname for clock1 above is top.test.clock1, the full pathname for variable a1 is top.test.clock1.a1.

A clocking block only describes how the inputs and outputs are sampled and synchronized. It does not assign a value to a variable. That is left to a module, interface or program that the clocking module is part of. While the parent block of a clocking module properly assigns a value to a variable, a clocking block defines how inputs are sampled and outputs are synchronized for its parent module. This is why an input or output declaration inside a clocking block does not need to specify any data width since it is only relevant if you assign a value to a variable or read from it.

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SystemVerilog Modports

Modports in SystemVerilog are used to restrict interface access within a interface. The keyword modport indicates that the directions are declared as if inside the module.

Modports can have

• input : Ports that need to be input.
• output : Ports that need to be output.
• inout : Ports that need to be inout
• ref : Ports that need to be ref.

Few of the examples usages of modports are, we can have interface file for

memory controller where, we can have

• Modports for memory
• Modports for system side
• Modports for testbench

Adding modports to an interface does not require that any of the modports be used when the interface is used. If no modport is specified in the module header or in the port connection, then all the nets and variables in the interface are accessible with direction inout or ref, Below example shows this in greater detail.

 //+++++++++++++++++++++++++++++++++++++++++++++++++
 // Define the interface
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 interface mem_if (input wire clk);
   logic        reset;
   logic        we_sys;
   logic        cmd_valid_sys;
   logic        ready_sys;
   logic  [7:0] data_sys;
   logic  [7:0] addr_sys;
   logic        we_mem;
   logic        ce_mem;
   logic  [7:0] datao_mem;
   logic  [7:0] datai_mem;
   logic  [7:0] addr_mem;
   //=================================================
   // Modport for System interface 
   //=================================================
   modport  system (input clk,reset,we_sys, cmd_valid_sys,
                    addr_sys, datao_mem, 
                    output we_mem, ce_mem, addr_mem, 
                    datai_mem, ready_sys, ref data_sys);
   //=================================================
   // Modport for memory interface 
   //=================================================
   modport  memory (input clk,reset,we_mem, ce_mem,
                    addr_mem, datai_mem, output datao_mem);
   //=================================================
   // Modport for testbench 
   //=================================================
   modport  tb (input clk, ready_sys, 
                output reset,we_sys, cmd_valid_sys, addr_sys, 
               ref data_sys);
 
 endinterface
 
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 //  Memory Model 
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 module memory_model (mem_if.memory mif);
 // Memory array
 logic [7:0] mem [0:255];
 
 //=================================================
 // Write Logic
 //=================================================
 always @ (posedge mif.clk)
  if (mif.ce_mem && mif.we_mem) begin
    mem[mif.addr_mem] <= mif.datai_mem;
  end
 
 //=================================================
 // Read Logic
 //=================================================
 always @ (posedge mif.clk)
  if (mif.ce_mem && ~mif.we_mem)  begin
    mif.datao_mem <= mem[mif.addr_mem];
  end
 
 endmodule
 
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 //  Memory Controller
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 module memory_ctrl (mem_if.system sif);
 
 typedef  enum {IDLE,WRITE,READ,DONE} fsm_t;
 
 fsm_t state;
 
 always @ (posedge sif.clk)
   if (sif.reset) begin
     state         <= IDLE;
     sif.ready_sys <= 0;
     sif.we_mem    <= 0;
     sif.ce_mem    <= 0;
     sif.addr_mem  <= 0;
     sif.datai_mem <= 0;
     sif.data_sys  <= 8'bz;
   end else begin
     case(state)
        IDLE :  begin
          sif.ready_sys <= 1'b0;
          if (sif.cmd_valid_sys && sif.we_sys) begin
            sif.addr_mem   <= sif.addr_sys;
            sif.datai_mem  <= sif.data_sys;
            sif.we_mem     <= 1'b1;
            sif.ce_mem     <= 1'b1;
            state          <= WRITE;
          end
          if (sif.cmd_valid_sys && ~sif.we_sys) begin
            sif.addr_mem   <= sif.addr_sys;
            sif.datai_mem  <= sif.data_sys;
            sif.we_mem     <= 1'b0;
            sif.ce_mem     <= 1'b1;
            state          <= READ;
          end
        end
        WRITE : begin
          sif.ready_sys  <= 1'b1;
          if (~sif.cmd_valid_sys) begin
            sif.addr_mem   <= 8'b0;
            sif.datai_mem  <= 8'b0;
            sif.we_mem     <= 1'b0;
            sif.ce_mem     <= 1'b0;
            state          <= IDLE;
          end
        end 
        READ : begin
          sif.ready_sys  <= 1'b1;
          sif.data_sys   <= sif.datao_mem;
          if (~sif.cmd_valid_sys) begin
            sif.addr_mem   <= 8'b0;
            sif.datai_mem  <= 8'b0;
            sif.we_mem     <= 1'b0;
            sif.ce_mem     <= 1'b0;
            sif.ready_sys  <= 1'b1;
            state          <= IDLE;
            sif.data_sys   <= 8'bz;
          end 
        end 
     endcase
   end
 
 endmodule
 
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 // Test  program
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 program test(mem_if.tb tif);
 
    initial begin
       tif.reset <= 1;
       tif.we_sys <= 0;
       tif.cmd_valid_sys <= 0;
       tif.addr_sys <= 0;
       tif.data_sys <= 8'bz;
        #100  tif.reset <= 0;
       for (int i = 0; i < 4; i ++) begin
          @ (posedge tif.clk);
          tif.addr_sys <= i;
          tif.data_sys <= $random;
          tif.cmd_valid_sys <= 1;
          tif.we_sys <= 1;
          @ (posedge tif.ready_sys);
          $display("@%0dns Writing address %0d with data %0x", 
              $time, i,tif.data_sys);
          @ (posedge tif.clk);
          tif.addr_sys <= 0;
          tif.data_sys <= 8'bz;
          tif.cmd_valid_sys <= 0;
          tif.we_sys <= 0;
       end
       repeat (10) @ (posedge tif.clk);
       for (int i= 0; i < 4; i ++) begin
          @ (posedge tif.clk);
          tif.addr_sys <= i;
          tif.cmd_valid_sys <= 1;
          tif.we_sys <= 0;
          @ (posedge tif.ready_sys);
          @ (posedge tif.clk);
          $display("@%0dns Reading address %0d, Got data %0x", 
            $time, i,tif.data_sys);
          tif.addr_sys <= 0;
          tif.cmd_valid_sys <= 0;
       end
        #10  $finish;
    end
 
 endprogram
 
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 //  Testbench
 //+++++++++++++++++++++++++++++++++++++++++++++++++
 module interface_modports();
 
 logic clk = 0;
 always  #10  clk++;
 //=================================================
 // Instianciate Interface and DUT 
 //=================================================
 mem_if miff(clk);
 memory_ctrl U_ctrl(miff);
 memory_model U_model(miff);
 test   U_test(miff);
 
 endmodule

You could download file interface_modports.sv here

 

Simulation Result : Modport

 @150ns Writing address 0 with data 24
 @230ns Writing address 1 with data 81
 @310ns Writing address 2 with data 9
 @390ns Writing address 3 with data 63
 @690ns Reading address 0, Got data 24
 @770ns Reading address 1, Got data 81
 @850ns Reading address 2, Got data 9
 @930ns Reading address 3, Got data 63

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Is ReRAM the end of NAND flash?

A primary storage technology: ReRAM.

NAND flash stores data in a little cloud of electrons in a quantum well. The presence or absence of charge - or the strength of the charge - tells us what bits are stored.

ReRAM stores data through changes in the resistance of a cell. There are a variety of ReRAM technologies in development, including phase-change memory (PCM) and HP's memristors, based on at least a half-dozen competing materials.

Expect healthy competition as the industry and buyers sort out the details.

Advantages

While different implementations have different specs, all ReRAM has key advantages over today's common NAND flash.

• Speed. ReRAM can be written much faster - in nanoseconds rather than milliseconds - making it better for high-performance applications.
• Endurance. MLC flash - the most common - can only handle about 10,000 writes. ReRAM can handle millions.
• Power. Researchers have demonstrated micro-Amp write power and expect to get in the nano-Amp range soon, which makes ReRAM much more power efficient than NAND flash, which requires voltage pumps to achieve the 20 volts required for writes.

The Storage Bits take

NAND flash will retain advantages in cost and density for the foreseeable future, meaning that it will be here for decades to come. So where will ReRAM fit in the storage hierarchy?

• Data integrity. Losing a snapshot is no big deal. Losing your checking account deposit is. Mission critical applications will prefer ReRAM devices - and can afford them.
• Performance. Today's SSDs go through many contortions to give good performance - and don't succeed all that well. A fast medium removes complexity as well as increasing performance.
• Mobility. Depending on how the never-ending tug-of-war between network bandwidth and memory capacity develops, consumers may come to prefer large capacity storage on their mobile devices. If so, ReRAM's power-sipping ways will be an asset on high-end products.

Toshiba is well-positioned to enter these high-end markets with SSDs analogous to today's 15k disks. It may not be a huge market, but the margins will make it worthwhile.

Other vendors, including Panasonic, Micron and Samsung, are also working on ReRAM products. Another interesting question: to what extent will fast ReRAM replace DRAM in systems?

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SEMI Industry spending $32.4B this year on IC gear

Fab equipment spending saw a drastic dip in 2H12 and 1Q13 is expected to be even lower, says SEMI, which reckons that the projected number of facilities equipping will drop from 212 in 2012 to 182 in 2013.

Spending on fab equipment for System LSI is expected to drop in 2013. Spending for Flash declined rapidly in 2H12 (by over 40 %) but is expected to pick up by 2H13. The foundry sector is expected to increase spending in 2013, led by major player TSMC, as well as Samsung and Global foundries.

Fab construction:
While fab construction spending slowed in 2012, at -15%,  SEMI  projects an increase of 3.7 % in 2013 (from $5.6bn in 2012 to $5.8bn  in 2013).

The report tracks 34 fab construction projects for 2013 (down from 51 in 2012).  An additional 10 new construction projects with various probabilities may start in 2013. The largest increase for construction spending in 2013 is expected to be for dedicated foundries and Flash related facilities.

Many device manufacturers are hesitating to add capacity due to declining average selling prices and high inventories.

However SEMI reckons flash capacity will grow 6%  by mid-2013, with nearly 6 % growth, adding over 70,000wpm.

SEMI also foresees a rapid increase of installed capacity for new technology nodes, not only for 28nm but also from 24nm to 18nm and first ramps for 17nm to 13nm in 2013.

SEMI cautiously forecasts  fab equipment spending in 2013 to range from minus 5 to plus 3.

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Full Speed Ahead For FPGA

In the world of high-frequency trading, where speed matters most, technology that can gain a crucial split-second advantage over a rival is valued above all others.

And in what could be the next phase of HFT, firms are looking more and more to hardware solutions, such as field-programmable gate array (FPGA), as it can offer speed gains on the current software used by HFT firms.

FPGA technology, which allows for an integrated circuit to be designed or configured after manufacturing, has been around for decades but has only been on the radar of HFT firms for a couple of years. But new solutions are beginning to pop up that may eventually see FPGA become more viable and be the latest must-have tool in the high-speed arms race.

For instance, a risk calculation that can take 30 microseconds to perform by a software-based algorithm takes just three microseconds with FPGA.

Current HFT platforms are typically implemented using software on computers with high-performance network adapters. However, the downside of FPGA is that it is generally complicated and time consuming to set up, as well as to re-program, as the programmer has to translate an algorithm into the design of an electronic circuit and describe that design in specialized hardware description language.

The programming space on FPGA is also limited, so programs can’t be too big currently. Although, some tasks such as ‘circuit breakers’ are an ideal current use for FPGA technology.

It is the drawbacks, as well as the costs involved, that are, at present, are holding back trading firms from taking up FPGA in greater numbers. However, because of the speed gains that it offers, much resources are being poured into FPGA in a bid to make the technology more accessible—and some technology firms are now beginning to claim significant speed savings with their products.

Cheetah Solutions, a provider of hardware solutions for financial trading, is one firm that says it can now offer reconfigurable FPGA systems to trading firms. It says its Cheetah Framework provides building blocks which can be configured in real time by a host server and an algorithm can execute entirely in an FPGA-enabled network card with the server software taking only a supervisory role by monitoring the algo’s performance and adapting the hardware algo on the go.

“True low latency will only be achieved through total hardware solutions which guarantee deterministic low latency,” said Peter Fall, chief executive of Cheetah Solutions. “But if the market moves, you want to be able to tweak an algorithm or change it completely to take advantage of current conditions. Traditional FPGA programming may take weeks to make even a simple change whereas Cheetah Framework provides on-the-fly reconfigurability.”

Another technology firm to claim that it can make automated trading strategies even faster and more efficient is U.K.-based Celoxica, which recently debuted its new futures trading platform, based on FPGA technology, which involves a circuit on one small chip that can be programmed by the customer.

Celoxica says the platform is designed to accelerate the flow of market data into trading algorithms to make trading faster. It covers multiple trading strategies and asset classes including fixed income, commodities and foreign exchange.

“For futures trading, processing speed, determinism and throughput continue to play a crucial role in the success of principle trading firms and hedge funds trading on the global futures markets,” said Jean Marc Bouleier, chairman and chief executive at Celoxica. “Our clients and partners can increase focus on their trading strategies for CME, ICE, CFE, Liffe US, Liffe and Eurex.”

While last August, Fixnetix, a U.K. trading technology firm, said that it had signed up a handful of top-tier brokers to use its FPGA hardware chip, which executes deals, compliance and risk checks, suggesting that this niche technology is picking up speed rapidly.