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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Tuesday, 12 May 2015

Ethernet

VLSI_ETHERNETEthernet has been a relatively inexpensive, reasonably fast, and very popular LAN technology for several decades. Two individuals at Xerox PARC -- Bob Metcalfe and D.R. Boggs -- developed Ethernet beginning in 1972 and specifications based on this work appeared in IEEE 802.3 in 1980. Ethernet has since become the most popular and most widely deployed network technology in the world. Many of the issues involved with Ethernet are common to many network technologies, and understanding how Ethernet addressed these issues can provide a foundation that will improve your understanding of networking in general.

The Ethernet standard has grown to encompass new technologies as computer networking has matured. Specified in a standard, IEEE 802.3, an Ethernet LAN typically uses coaxial cable or special grades of twisted pair wires. Ethernet is also used in wireless LANs. Ethernet uses the CSMA/CD access method to handle simultaneous demands. The most commonly installed Ethernet systems are called 10BASE-T and provide transmission speeds up to 10 Mbps. Devices are connected to the cable and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. Fast Ethernet or 100BASE-T provides transmission speeds up to 100 megabits per second and is typically used for LAN backbone systems, supporting workstations with 10BASE-T cards. Gigabit Ethernet provides an even higher level of backbone support at 1000 megabits per second (1 gigabit or 1 billion bits per second). 10-Gigabit Ethernet provides up to 10 billion bits per second.

The Ethernet standard has grown to encompass new technologies as computer networking has matured. Specified in a standard, IEEE 802.3, an Ethernet LAN typically uses coaxial cable or special grades of twisted pair wires. Ethernet is also used in wireless LANs. Ethernet uses the CSMA/CD access method to handle simultaneous demands. The most commonly installed Ethernet systems are called 10BASE-T and provide transmission speeds up to 10 Mbps. Devices are connected to the cable and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. Fast Ethernet or 100BASE-T provides transmission speeds up to 100 megabits per second and is typically used for LAN backbone systems, supporting workstations with 10BASE-T cards. Gigabit Ethernet provides an even higher level of backbone support at 1000 megabits per second (1 gigabit or 1 billion bits per second). 10-Gigabit Ethernet provides up to 10 billion bits per second.

 

Sunday, 15 March 2015

A Cache Memory

Today we feel to revise what we know about cache memory. A cache is a memory device that improves performance of the processor by transparently storing data such that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere.



Access to cache can result in either one of the following: cache miss or cache hit.Cache hit means that the requested data is contained in the cache and cache miss means data is not found there in cache.On cache hit processor takes data from cache itself for processing.On cache miss the data is fetched from the original memory location.Cache memories are volatile and small in storage size.Since the storage size is small the address decoding takes less time and hence caches are faster then normal physical memories(RAM's) in computers.

As I said the data is stored transparently in cache.This means that the user who is requesting data from the cache need not know whether data is stored in cache or system memory.It is handled by the processor.The word cache means "conceal" in French.


A simple cache contains three fields.

1. An index which is local to the cache.
2. A tag which is the index with reference to the main memory.This will let the processor know the location in main memory where an exact copy of data is stored.
3. Data, which is actual data needed by the processor.


When processor needs some data from the memory it first checks in cache.It sees all the tag fields in the cache to see whether same data is available in cache.If the tag is found then the corresponding data is taken.Otherwise a cache miss error is asserted and the main memory is accessed.Also the cache memory is updated with the recent memory access.This is called cache update on cache miss.


During a cache update if the cache is full, then it has to delete a row.This is decided on a cache replacement algorithm.Some algorithms are:

1. LRU - Least recently used data is replaced.
2. MRU - Most recently used data is replaced.
3. Random replacement - Simple, used in ARM processors.
4. Belady's Algorithm - discards the data which may not be used for the longest time in future.Not perfectly implementable in practice.


The average memory access time of a cache enabled system can be calculated using the hit and miss ratio of a cache.

Average memory access time = (Time_cache * Hit_counts ) + ( (Time_cache + Time_mm) * Miss_counts)

where,
Time_cache and Time_mm is the time needed to access a location for cache and main memory respectively.
Hit_counts and Miss_counts are the hit and miss probabilities.


There are two types cache writing: write back(copy-back) and write through.

When the data at a particular memory location is updated then this data must be written back to cache.If the data is updated only in the cache then it is called write back.If the updating of data happens both in cache and main memory then it is called write through.Write through keeps the cache and memory synchronized.In the write back operation since the cache data is not same as the main memory data it is marked as "dirty" data.These dirty data will be written back into main memory when the particular data is cleared from the cache.If a miss happens in a write-back cache it may sometimes require two memory accesses to service : one to first write the dirty location to memory and then another to read the new location from memory.

The main memory locations may be altered without proper updating in cache by peripherals using DMA or by a multi core processor.This results in a out of date data in cache.These type of data is called "stale" data.To solve these stale data problems we have to use cache coherence protocols between the cache managers to keep the data consistent.


All caches are CAM(content accessible memory).And for efficiency we have to scan all the memory contents in one cycle.This requires parallel hardware.Also higher the memory size the more is the memory access time.

Let us see now,how a cache is made.Say we have a 32 bit main memory in our system and the cache chip size is 4 Kb.Also say each line in cache stores 32 bytes so that there are totally 128 lines.Each line in cache have two fields. Address(4 bytes) and Data.The address is further divided into two fields- Tag(27 bits) and offset(5 bits for indexing a particular byte among the data).Remember that the tag contain the MSB 27 bits of the address here.These kind of caches are called Fully associative caches.Since the tag is 27 bits(relatively long) it takes more time to read data from Fully associative cache.Also more hardware circuit is required for parallel reading of tags from the CAM type cache.So they are expensive but more efficient.

Fully associative cache


Another type of cache architecture is known as direct mapped cache.In this the address is divided into three fields named tag(20 bits),index(7 bits used as an index the 128 lines in cache) and offset(5 bits).The problem with this type of cache is that the cache is less efficient since the main memory cannot be copied to any line in cache as in fully associative cache.This is because the addresses with the same index will be mapped to the same line in cache.But the cache access time is less here.In certain situations you may get a cache miss for almost every access.So they are cheap but less efficient.

Direct mapped Cache
Another type of cache is called set associative cache which has the advantages of both direct mapped and fully associative caches.These are again subdivided based on the number of bits in the index field.

2. 2 way set associative cache - In this type of cache we have two group of lines,each containing 64 lines.The cache has the same number of fields as direct mapped cache but tag has 21 bits and index has 6 bits here.


2. 4 way set associative cache - Here we have 4 groups each contains 32 lines.index has 5 bits and tag has 22 bits.

2-way and 4-way set associative caches

Sunday, 1 March 2015

SystemVerilog Associative Arrays

In previous post we learn in detail about SystemVerilog Dynamic arrays which is useful for dealing with contiguous collections of variables whose number changes dynamically. Now consider if the size of array is unknown then how much size will you allocate to array?

An Associative array is one to use when the size of the collection is unknown or the data space is sparse. So the associative arrays are mainly used to model the sparse memories. In the associative arrays the storage is allocated only when we use it not initially like in dynamic arrays. Associative arrays can be assigned only to another Associative array of a compatible type and with the same index type.

Another main difference between Associative array and normal arrays is in that in assoc arrays the arrays index can be any scalar value. 

Properties of Associative arrays:
  • Dynamically allocated, non-contiguous elements
  • Accessed with integer, or string index, single dimension
  • Great for sparse arrays with wide ranging index
  • Array functions: exists, first, last, next, prev
Declaration Syntax:

data_type array_name [ index_type ];

Where,
data_type : data type of the array element. This can be any type that is allowed for Fixed Arrays
array_name : name of the array being declared.
index_type : data type to be used as index

Example : Associative array declaration

int array_name[*];//Wildcard index. can be indexed by any integral datatype.
int array_name [string];// String index
int array_name [some_Class];// Class index
int array_name [integer];// Integer index
typedef bit signed [4:1] Nibble;
int array_name [Nibble]; // Signed packed array

Accessing the Associative arrays
SystemVerilog provides various in-built methods to access, analyze and manipulate the associative arrays.
  • num() or size() returns the number of entries in the associative arrays.
  • delete() removes the entry from specified index.
  • exist() checks weather an element exists at specified index of the given associative array.
  • first() assigns to the given index variable the value of the smallest/first index in the associative array. Returns 0 if array is empty; else returns 1.
  • last() assigns to the given index variable the value of the largest/last index in the associative array. Returns 0 if array is empty; else returns 1.
  • next() finds the entry whose index is greater than the given index. If next entry exists then the index variable is assigned to the index of next entry and returns 1. Otherwise the index is unchanged and the function returns 0.
  • previous() finds the entry whose index is smaller than the given index. If previous entry exists then the index variable is assigned to the index of previous entry and returns 1. Otherwise the index is unchanged and the function returns 0.

Example : Associative Arrays in-built methods

// SystemVerilog Associative arrays
module associative_array ();
 
 integer associative_array [integer];
 
 integer i;
 
 initial begin
   // Add element array
   associative_array[100] = 101;
   $display ("value stored in 100 is %d", associative_array[100]);
   associative_array[1]   = 100;
   $display ("value stored in 1   is %d", associative_array[1]);
   associative_array[50]   = 99;
   $display ("value stored in 50  is %d", associative_array[50]);
   associative_array[250] = 22;
   $display ("value stored in 250 is %d", associative_array[250]);
   // Print the size of array
   $display ("size of array is %d", associative_array.num());
   // Check if index 2 exists
   $display ("index 2 exists   %d", associative_array.exists(2));
   // Check if index 100 exists
   $display ("index 100 exists %d", associative_array.exists(100));
   // Value stored in first index
   if (associative_array.first(i)) begin
     $display ("value at first index %d value %d", i, associative_array[i]);
   end
   // Value stored in last index
   if (associative_array.last(i)) begin
     $display ("value at last index  %d value %d", i,  associative_array[i]);
   end
   // Delete the first index
   associative_array.delete(100);
   $display ("Deleted index 100");
   // Value stored in first index
   if (associative_array.first(i)) begin
     $display ("value at first index %d value %d", i, associative_array[i]);
   end
    #1  $finish;
 end
 
 endmodule

Simulation Result:
value stored in 100 is 101
value stored in 1 is 100
value stored in 50 is 99
value stored in 250 is 22
size of array is 4
index 2 exists 0
index 100 exists 1
value at first index 1 value 100
value at last index 250 value 22
Deleted index 100
value at first index 1 value 100

Try simulation yourself here

Now as you know that we can use any data type as index of associative arrays, below are the things to keep in mind while using different index datatypes.

1. Integer or int index : While using integer in associative arrays, following rules need to be kept in mind.

  • A 4-state index containing X or Z is invalid.
  • Indices smaller than integer are sign extended to 32 bits.
  • The ordering is signed numerical.
  • Indices can be any integral expression.
  • Indices are signed.
  • Example: int array_name [ integer ];

2. String index : While using string in associative arrays, following rules need to be kept in mind.

  • An empty string "" index is valid.
  • The ordering is lexicographical (lesser to greater).
  • Indices can be strings or string literals of any length.
  • Example: int array_name [ string ];

3. Class index : While using class in associative arrays, following rules need to be kept in mind.
  • A null index is valid.
  • The ordering is deterministic but arbitrary.
  • Indices can be objects of that particular type or derived from that type.
  • Example: int array_name [ some_Class ];

4. Wild Character index : While using wild characters in associative arrays, following rules need to be kept in mind.
  • A 4-state Index containing X or Z is invalid.
  • Indices are unsigned.
  • Indexing expressions are self-determined; signed indices are not sign extended.
  • The ordering is numerical (smallest to largest).
  • A string literal index is auto-cast to a bit-vector of equivalent size.
  • The array can be indexed by any integral data type.
  • Example: int array_name [*];

Saturday, 14 February 2015

eInfochips, Toshiba to jointly build chips for Google's modular phones

Ahmedabad-based tech firm eInfochips has tied up with Toshiba to jointly build and design chips for 'Spiral' range of Google's first modular smartphones. Modular phones are customisable smartphones wherein users can add or remove hardware-cum-software modules based on their requirement.

The firms have jointly developed chips for the base plate of the smartphone as well as chips for potential modules. Among the Spiral range of phone, Google is likely to launch Spiral-3, the third edition of the modular smartphones by mid-2015, it has been learnt. The third edition Spiral-3 is a modular mobile phone prototype under Google's 'Project Ara'.


They could add a sensor to test if water is clean. They could have a battery that lasts for days. They could have a louder speaker, gaming console, or use the smartphone as their car key. The possibilities are endless. To enable modular smartphones, eInfochips and TAEC offer the ARTOS12 Google Ara Development Kit for the 1x2 Module that uses Toshiba bridge chip technology and eInfochips engineering services.

The kit features MicroSD and USB slots enabling developers to store data and interface to external devices.  The Toshiba T6WR6XBG general-purpose bridge used in the development kit supports optional interfaces such as UART, I2C, I2S, SPI, and GPIO on the 1x2 module. The Ara 1x2 module development kit also includes high-speed interfaces for connection to the application processor bridge, USB drivers and quick-start documentation. Engineering services, distribution, support, release management and product delivery of ARTOS12 Google Ara development kits is provided by eInfochips.
eInfochips, in addition to being the development and support collaborator for the ARTOS12 Development Kit, will also offer its expertise on Google Ara modules with custom design and engineering services. These include platform porting, multimedia integration, application development, and performance optimization, among others. Companies seeking first-mover advantage on Google Ara modules can leverage eInfochips experience in this domain to accelerate development cycles. Having contributed to over 500+ hardware and software product designs, eInfochips can address gaps in the development of Project Ara smartphone module hardware and software.
According to Parag Mehta, Chief Marketing and Business Development Officer at eInfochips, “eInfochips is one of a handful of global engineering services companies with the experience in hardware, software and system design needed to deliver world-class Project Ara smartphone modules.”
"This will enable companies and individuals to design and innovative modules. This will be much similar to what emergence of mobile applications did for millions of software developers," said Kazi.
The smartphone will have Android platform and will come in three different sizes. The modules, categorized in three dimensions with 1x1 inch, 1x2 inch and 2x2 inches, will be certified by Google. The patent and IPR rights of the phone will remain with Google.
Already 20-30 large global corporations are working for different modules including camera, memory, display, speakers among others.

Friday, 30 January 2015

SystemVerilog Linked Lists

Linked lists and arrays are similar since they both store collections of data. The terminology is that arrays and linked lists store "elements" on behalf of "client" code. The specific type of element is not important since essentially the same structure works to store elements of any type. One way to think about linked lists is to look at how arrays work and think about alternate approaches.

The List package implements a classic list data-structure, and is analogous to the STL (Standard Template Library) List container that is popular with C++ programmers. The container is defined as a parametrized class, meaning that it can be customized to hold data of any type. The List package supports lists of any arbitrary predefined type, such as integer, string, or class object. First declare the Linked list type and then take instances of it. SystemVerilog has many methods to operate on these instances. 

A double linked list is a chain of data structures called nodes. Each node has 3 members, one points to the next item or points to a null value if it is last node, one points to the previous item or points to a null value if it is first node and other has the data. 

Difference between Queue and Linked list:

A queue can pretty much do anything a linked listed can do, and more efficiently. The only case where a linked list might be more efficient is when you need to join two lists together, or insert one list in the middle of another list. A queue is very efficient for adding one element at a time.

Previous : SystemVerilog Queue
Next :

Thursday, 29 January 2015

SystemVerilog Queue

Queue is a variable size, ordered collection of homogeneous elements which can grow and shrink. The size of a queue is variable similar to a dynamic array, but a queue may be empty with no element and it is still a valid data structure. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In First Out) type of buffers.

Syntax:
A queue is declared simply by putting a $ as the size of an array.
integer my_q[$];

You can initialize a queue at the place of its variable declaration:
integer my_q[$] = {1, 3, 5};

You can also set up an upper limit of index for a queue (a bounded queue):
integer my_q[$:127];

Since index of an array can only be non-negative, the maximum number of elements for the queue in the above case is 128 (i.e., 0 through 127).

Each element in the queue is identified by an ordinal number that represents its position within the queue, with 0 representing the first element and $ represents the last element.

Bounded Queues
Size of a queue can be limited by giving the last index (i.e. upper bound) as follows

int queueA[$:99]; // A queue whose maximum size is 100 integers 

These are called bounded queues.It will not have an element whose index is higher than the queue’s declared upper bound. Operators on bounded queue can be applied exactly the same way as unbounded queues, except that, result should fall in the upper bound limit.

The size of the queue is variable similar to dynamic array but queue may be empty with zero element and still its a valid data structure.

Queues and dynamic arrays have the same assignment and argument passing semantics. Also, queues support the same operations that can be performed on unpacked arrays and use the same operators and rules except as defined below:


// SystemVerilog Queue Operations
int q[$] = { 2, 4, 8 }; 
int p[$]; 
int e, pos; 
e = q[0]; // read the first (leftmost) item 
e = q[$]; // read the last (rightmost) item 
q[0] = e; // write the first item 
p = q; // read and write entire queue (copy) 
q = { q, 6 }; // insert '6' at the end (append 6) 
q = { e, q }; // insert 'e' at the beginning (prepend e) 
q = q[1:$]; // delete the first (leftmost) item 
q = q[0:$-1]; // delete the last (rightmost) item 
q = q[1:$-1]; // delete the first and last items 
q = {}; // clear the queue (delete all items) 
q = { q[0:pos-1], e, q[pos,$] }; // insert 'e' at position pos 
q = { q[0:pos], e, q[pos+1,$] }; // insert 'e' after position pos 

Queue Methods:

Queues also provides several built-in methods to access/modify queue. Below we have list down all such methods.
  • The size() method returns the number of items in the queue. If the queue is empty, it returns 0. 
  • The insert() method inserts the given item at the specified index position. 
  • The delete() method deletes the item at the specified index. 
  • The pop_front() method removes and returns the first element of the queue. 
  • The pop_back() method removes and returns the last element of the queue. 
  • The push_front() method inserts the given element at the front of the queue. 
  • The push_back() method inserts the given element at the end of the queue. 

// SystemVerilog Queue Methods
module queue_methods();

// Queue is declated with $ in array size
  integer queue[$] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
integer i;

initial begin
  $display ("Initial elements in the queue");
  print_queue;
  // Insert new element at begin of queue
  queue = {11, queue};
  $display ("new element added using concatenation");
  print_queue;
  // Insert using method at beginning
  queue.push_front(12);
  $display ("new element added using push_front");
  print_queue;
  // Insert using method at end
  queue.push_back(12);
  $display ("new element added using push_back");
  print_queue;
  // Using insert to insert, here 6 is index
  // and 13 is value
  queue.insert(6,13);
  $display ("new element added using insert(index,value)");
  print_queue;
  // get first queue element method at begining
  i = queue.pop_front();
  $display ("element poped using pop_front");
  print_queue;
  // get last queue element method at end
  i = queue.pop_back();
  $display ("element poped using pop_end");
  print_queue;
  // Use delete method to delete element at index 4 in queue
  queue.delete(10);
  $display ("deleted element at index 10");
  print_queue;
  #1 $finish;
end

  // Method to print queue
task print_queue;
  integer i;
  $write("Queue contains ");
  for (i = 0; i < queue.size(); i ++) begin
    $write (" %g", queue[i]);
  end
  $write("\n");
endtask

endmodule

Results:
Initial elements in the queue
Queue contains  0 1 2 3 4 5 6 7 8 9 10
new element added using concatenation
Queue contains  11 0 1 2 3 4 5 6 7 8 9 10
new element added using push_front
Queue contains  12 11 0 1 2 3 4 5 6 7 8 9 10
new element added using push_back
Queue contains  12 11 0 1 2 3 4 5 6 7 8 9 10 12
new element added using insert(index,value)
Queue contains  12 11 0 1 2 3 13 4 5 6 7 8 9 10 12
element poped using pop_front
Queue contains  11 0 1 2 3 13 4 5 6 7 8 9 10 12
element poped using pop_end
Queue contains  11 0 1 2 3 13 4 5 6 7 8 9 10
deleted element at index 10
Queue contains  11 0 1 2 3 13 4 5 6 7 9 10

Try simulation yourself here

Hope you get the idea how to declare and use the SystemVerilog Queues. Next we will learn about Linked lists, array methods and we will compare the array types in SystemVerilog.

Previous : SystemVerilog Associative Arrays
Next : SystemVerilog Linked Lists

Wednesday, 28 January 2015

SystemVerilog Dynamic Arrays

In this SystemVerilog Tutorial so far we have seen basic array type i.e. SystemVerilog Fixed arrays, as its size is set at compile time. 

Now what if you don't know the size of array until run-time? 

You may wish to set the size of array run-time and wish to change the size dynamically during run time. 

For example an IP packet varies length from one packet to other packet. In verilog, for creating such packet, array with maximum packet size is declared and only the number of elements which are require for small packets are used and unused elements are waste of memory. 

SystemVerilog overcomes this problem and provides us dynamic arrays. 

Following are the features of SystemVerilog Dynamic arrays :

1. Size of dynamic array can be set at runtime.
2. Previously set size of the dynamic array can be changed runtime without loosing the previous contents.

Hence, dynamic array is unpacked array whose size can be allocated run time along with the option to resize.

Declaration of SystemVerilog Dynamic Arrays :
Dynamic arrays are declared with empty word subscript [ ].


1
2
3
integer dyn_array_1[];
integer dyn_array_1[];
integer multi_dime_dyn_array[][]; 

Allocating size of Dynamic Array :
As seen above the dynamic array is declared with empty word subscript [ ], which means you do not wish to allocate size at compile time, instead, you specify the size at runtime.

The dynamic arrays used builtin function new[ ] to allocate the storage and initialize the newly allocated array.


// SystemVerilog Dynamic arrays
module dyn_arr;
  int dyn[], d2[];             // Empty dynamic arrays
  initial begin
    dyn = new[5];              // Allocate 5 elements
    foreach (dyn[j]) begin
      dyn[j] = j;              // Initialize the elements
      $display("j = %0d dyn = %0d",j,dyn[j]); 
    end
    $display("Copy the dynamic array");
    
    // Copy a dynamic array
    d2 = dyn;
    $display("dyn[0] = %0d d2[0] = %0d",dyn[0],d2[0]);
    
    $display("Modify contents of copy");
    // Modify the copy
    d2[0] = 5;                 
    $display("dyn[0] = %0d d2[0] = %0d",dyn[0],d2[0]);
    
    $display ("Extend the array length and check previous content");
    // Expand and copy
    dyn = new[20](dyn);
    $display("dyn[4] = %0d", dyn[4]);
    
    $display ("Extend the array length and check previous content");
    // Allocate 100 new integers. Old values will lost
    dyn = new[100];    
    $display ("dyn[4] = %0d", dyn[4]);
    // Delete all elements
    dyn.delete;   
  end
endmodule

Simulation result :
j = 0 dyn = 0
j = 1 dyn = 1
j = 2 dyn = 2
j = 3 dyn = 3
j = 4 dyn = 4
Copy the dynamic array
dyn[0] = 0 d2[0] = 0
Modify contents of copy
dyn[0] = 0 d2[0] = 5
Extend the array length and check previous content
dyn[4] = 4
Extend the array length and check previous content
dyn[4] = 0

Run Simulation

Methods associated with Dynamic arrays :

.size() : Returns the size of dynamic array. We can also use system task $size() method instead of .size() method.

.delete() : SystemVerilog also provides .delete() method clears all the elements yielding an empty array (zero size).


Previous : Fixed Size Arrays
Next : Associative Arrays