library ieee;
use ieee.std_logic_1164.all;
entity my_and is
port (a, b : in std_logic;
c : out std_logic);
end my_and;
architecture my_and_arc of my_and is
begin
c <= a and b;
end my_and_arc;
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
library ieee;
use ieee.std_logic_1164.all;
entity my_and is
port (a, b : in std_logic;
c : out std_logic);
end my_and;
architecture my_and_arc of my_and is
begin
c <= a and b;
end my_and_arc;