SystemVerilog Strings

String data type is used for storing strings, the size is dynamic and string data types come with build in methods. If you have ever tried to use a Verilog reg variable to hold a string of characters, your suffering is over with this post. The SystemVerilog string type holds variable-length strings. String literals are packed arrays of a width that is a multiple of 8 bits which hold ASCII values i.e. an individual character is of type byte. The elements of a string of length N are numbered 0 to N-1. Note that, unlike C, there is no null character at the end of a string, and any attempt to use the character “\0” is ignored.

string StringName = "VLSI Encyclopedia";

Strings use dynamic memory allocation, so you do not have to worry about running out of space to store the string. Example 1 shows various string operations.

Below is the list of string methods :

• str.len() returns the length of the string, i.e., the number of characters in the string. 
• str.putc(i, c) replaces the ith character in str with the given integral value. 
• str.getc(i) returns the ASCII code of the ith character in str. 
• str.toupper() returns a string with characters in str converted to uppercase. 
• str.tolower() returns a string with characters in str converted to lowercase. 
• str.compare(s) compares str and s, and return value. This comparison is case sensitive. 
• str.icompare(s) compares str and s, and return value .This comparison is case insensitive. 
• str.substr(i, j) returns a new string that is a substring formed by index i through j of str. 
• str.atoi() returns the integer corresponding to the ASCII decimal representation in str. 
• str.atoreal() returns the real number corresponding to the ASCII decimal representation in str. 
• str.itoa(i) stores the ASCII decimal representation of i into str (inverse of atoi). 
• str.hextoa(i) stores the ASCII hexadecimal representation of i into str (inverse of atohex). 
• str.bintoa(i) stores the ASCII binary representation of i into str (inverse of atobin). 
• str.realtoa(r) stores the ASCII real representation of r into str (inverse of atoreal)

Example 1: SystemVerilog String Methods

// SystemVerilog Strings
module str; 
  string S1; 
  string S2; 
  initial begin 
    S1 = "VLSI "; 
    S2 = "Encyclopedia"; 
    $display(" %d ",S1.len() ); 
    $display(" %s ",S2.getc(5) ); 
    $display(" %s ",S1.tolower); 
    $display(" %s ",S2.toupper); 
    $display(" %d ",S2.compare(S1) ); 
    $display(" %d ",S1.compare("VLSI") ); 
    $display(" %s ",S1.substr(2,3) ); S1 = "111"; 
    $display(" %d ",S1.atoi() ); 
  end 
endmodule 

Simulation Result :
 5
 l
 vlsi
 ENCYCLOPEDIA
 -17
 1
 SI
 111

Pattern Matching of SystemVerilog Strings
In below example we have used a method to match the strings in SystemVerilog.

Example 2 : Pattern matching

// SystemVerilog String Pattern Matching
 
program main; 
  string S1,S2; 
  initial begin 
    S1 = "String matching in SystemVerilog"; 
    S2 = "String"; 
    if(match(S1,S2)) 
      $display(" S2 : %s : found in :%s:",S2,S1); 

    S2 = "SystemVerilog"; 
    if(match(S1,S2)) 
      $display(" S2 : %s : found in :%s:",S2,S1); 

    S2 = "String matching"; 
    if(match(S1,S2)) 
      $display(" S2 : %s : found in :%s:",S2,S1); 

    S2 = "matching in "; 
    if(match(S1,S2)) 
      $display(" S2 : %s : found in :%s:",S2,S1); 

    S2 = "String matching in SystemVerilog"; 
    if(match(S1,S2)) 
      $display(" S2 : %s : found in :%s:",S2,S1); 
  end 
endprogram

function match(string s1,s2); 
  int len1,len2; 
  len1 = s1.len(); 
  len2 = s2.len(); 
  match = 0 ; 
  if( len2 > len1 ) 
    return 0; 
  for(int i = 0;i < len1 - len2 + 1; i ++) 
    if( s1.substr(i,i+len2 -1) == s2) 
  return 1; 
endfunction

Simulation Results:
 S2 : String : found in :String matching in SystemVerilog:
 S2 : SystemVerilog : found in :String matching in SystemVerilog:
 S2 : String matching : found in :String matching in SystemVerilog:
 S2 : matching in  : found in :String matching in SystemVerilog:
 S2 : String matching in SystemVerilog : found in :String matching in SystemVerilog:

SystemVerilog operations
There are variety of operations associated with SystemVerilog strings that you can perform to manipulate the  combination of string variables and string literals. Below are the basic operation that can be performed on strings.

1. Checking equality of two strings : S1 == S2
Checks whether the two strings are equal. Checking equality results 1 if they are equal and 0 if they are unequal. Both strings can be of type string. Or one of them can be a string literal. If both operands are string literals, the operator is the same Verilog equality operator as for integer types.

Example 3 : Checking Equality

// SystemVerilog Strings Equality
module str; 
  string S1 = "VLSI Encyclopedia"; 
  string S2 = "VLSI Encyclopedia";
  string S3 = "vlsi encyclopedia";
  initial begin 
    if(S1 == S2) 
      $display(" S1 and S2 are equal"); 
    else 
      $display(" S1 and S2 are not equal"); 
    if(S1 == S3) 
      $display(" S1 and S3 are equal"); 
    else 
      $display(" S1 and S3 are not equal"); 
  end 
endmodule 

Simulation Results 
S1 and S2 are equal
S1 and S3 are not equal

2. Checking equality of two strings : S1 != S2
Reverse to the equality operation this operation results 0 if two strings are equal and 1 if they are unequal.

Example 4: Checking Inequality

// SystemVerilog Strings Equality
module str; 
  string S1 = "VLSI Encyclopedia"; 
  string S2 = "VLSI Encyclopedia";
  string S3 = "vlsi encyclopedia";
  initial begin 
    if(S1 != S2) 
      $display(" S1 and S2 are not equal"); 
    else 
      $display(" S1 and S2 are equal"); 
    if(S1 != S3) 
      $display(" S1 and S3 are not equal"); 
    else 
      $display(" S1 and S3 are equal"); 
  end 
endmodule 

Simulation Results 
S1 and S2 are equal
S1 and S3 are not equal

3. Concatenation of strings : {S1, S2, S3,...,Sn}
To concatenate two or more strings, specify the string variable inside {} each separated by comma",". Each operand can be of type string or a string literal.

Example 5 : Concatenation

// SystemVerilog Strings Concatenation
module str; 
  string S1, S2, S3, S4, S5; 
  initial begin 
    S1 = "Con"; 
    S2 = "cate"; 
    S3 = ""; 
    S4 = "na"; 
    S5 = "tion"; 
    $display(" %s ",{S1,S2,S3,S4,S5}); 
  end 
endmodule 

Simulation Results
Concatenation

4. Replication of Strings : {N{S1}}
The result of replication is a string containing N concatenated copies of S1. N is the multiplier ans S1 can be of string type or string literal.

Example 6 : Replication

// SystemVerilog Strings Replication
module str; 
  string S1, S2; 
  initial begin 
    S1 = "w"; 
    S2 = ".vlsiencyclopedia.com"; 
    $display(" %s ",{{3{S1}},S2}); 
  end 
endmodule 

Simulation Results :
www.vlsiencyclopedia.com

5. String Indexing : S1[Index]
It returns a byte, an ASCII code at the given Index. Index can range from 0 to N where N is the number of characters in the string. If the Index is out of range then result will be 0.

Example 7 : Indexing

// SystemVerilog Strings Indexing
module str; 
  initial begin
    string S1; 
   S1 = "Indexing"; 
  for(int i =0 ;i < 8 ; i++) 
    $display("%s ",S1[i]); 
  end 
endmodule 

Simulation Result :
I
n
d
e
x
i
n
g

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