Logic Gates

Logic Gates
NOT	AND	OR	NAND	NOR	XOR	XNOR

Introduction to Digital Logic Gates

A Digital Logic Gate is an electronic device that makes logical decisions based on the different combinations of digital signals present on its inputs. Digital logic gates may have more than one input but generally only have one digital output. Individual logic gates can be connected together to form combinational or sequential circuits, or larger logic gate functions.

Standard commercially available digital logic gates are available in two basic families or forms, TTLwhich stands for Transistor-Transistor Logic such as the 7400 series, and CMOS which stands for Complementary Metal-Oxide-Silicon which is the 4000 series of chips. This notation of TTL or CMOS refers to the logic technology used to manufacture the integrated circuit, (IC) or a “chip” as it is more commonly called.

Generally speaking, TTL logic IC’s use NPN and PNP type Bipolar Junction Transistors while CMOS logic IC’s use complementary MOSFET or JFET type Field Effect Transistors for both their input and output circuitry.

As well as TTL and CMOS technology, simple Digital Logic Gates can also be made by connecting together diodes, transistors and resistors to produce RTL, Resistor-Transistor logic gates, DTL, Diode-Transistor logic gates or ECL, Emitter-Coupled logic gates but these are less common now compared to the popular CMOS family.

Integrated Circuits or IC’s as they are more commonly called, can be grouped together into families according to the number of transistors or “gates” that they contain. For example, a simple AND gate my contain only a few individual transistors, were as a more complex microprocessor may contain many thousands of individual transistor gates. Integrated circuits are categorised according to the number of logic gates or the complexity of the circuits within a single chip with the general classification for the number of individual gates given as:

Classification of Integrated Circuits

• Small Scale Integration or (SSI) – Contain up to 10 transistors or a few gates within a single package such as AND, OR, NOT gates.
• Medium Scale Integration or (MSI) – between 10 and 100 transistors or tens of gates within a single package and perform digital operations such as adders, decoders, counters, flip-flops and multiplexers.
• Large Scale Integration or (LSI) – between 100 and 1,000 transistors or hundreds of gates and perform specific digital operations such as I/O chips, memory, arithmetic and logic units.
• Very-Large Scale Integration or (VLSI) – between 1,000 and 10,000 transistors or thousands of gates and perform computational operations such as processors, large memory arrays and programmable logic devices.
• Super-Large Scale Integration or (SLSI) – between 10,000 and 100,000 transistors within a single package and perform computational operations such as microprocessor chips, micro-controllers, basic PICs and calculators.
• Ultra-Large Scale Integration or (ULSI) – more than 1 million transistors – the big boys that are used in computers CPUs, GPUs, video processors, micro-controllers, FPGAs and complex PICs.

While the “ultra large scale” ULSI classification is less well used, another level of integration which represents the complexity of the Integrated Circuit is known as the System-on-Chip or (SOC) for short. Here the individual components such as the microprocessor, memory, peripherals, I/O logic etc, are all produced on a single piece of silicon and which represents a whole electronic system within one single chip, literally putting the word “integrated” into integrated circuit.

These complete integrated chips which can contain up to 100 million individual silicon-CMOS transistor gates within one single package are generally used in mobile phones, digital cameras, micro-controllers, PIC’s and robotic type applications.

Moore’s Law

In 1965, Gordon Moore co-founder of the Intel corporation predicted that “The number of transistors and resistors on a single chip will double every 18 months” regarding the development of semiconductor gate technology. When Gordon Moore made his famous comment way back in 1965 there were approximately only 60 individual transistor gates on a single silicon chip or die.

The worlds first microprocessor in 1971 was the Intel 4004 that had a 4-bit data bus and contained about 2,300 transistors on a single chip, operating at about 600kHz. Today, the Intel Corporation have placed a staggering 1.2 Billion individual transistor gates onto its new Quad-core i7-2700K Sandy Bridge 64-bit microprocessor chip operating at nearly 4GHz, and the on-chip transistor count is still rising, as newer faster microprocessors and micro-controllers are developed.

Digital Logic States

The Digital Logic Gate is the basic building block from which all digital electronic circuits and microprocessor based systems are constructed from. Basic digital logic gates perform logical operations of AND, OR and NOT on binary numbers.

In digital logic design only two voltage levels or states are allowed and these states are generally referred to as Logic “1” and Logic “0”, High and Low, or True and False. These two states are represented in Boolean Algebra and standard truth tables by the binary digits of “1” and “0”respectively.

A good example of a digital state is a simple light switch as it is either “ON” or “OFF” but not both at the same time. Then we can summarise the relationship between these various digital states as being:

Boolean Algebra	Boolean Logic	Voltage State
Logic “1”	True (T)	High (H)
Logic “0”	False (F)	Low (L)

Most digital logic gates and digital logic systems use “Positive logic”, in which a logic level “0” or “LOW” is represented by a zero voltage, 0v or ground and a logic level “1” or “HIGH” is represented by a higher voltage such as +5 volts, with the switching from one voltage level to the other, from either a logic level “0” to a “1” or a “1” to a “0” being made as quickly as possible to prevent any faulty operation of the logic circuit.

There also exists a complementary “Negative Logic” system in which the values and the rules of a logic “0” and a logic “1” are reversed but in this tutorial section about digital logic gates we shall only refer to the positive logic convention as it is the most commonly used.

In standard TTL (transistor-transistor logic) IC’s there is a pre-defined voltage range for the input and output voltage levels which define exactly what is a logic “1” level and what is a logic “0” level and these are shown below.

TTL Input & Output Voltage Levels

There are a large variety of logic gate types in both the bipolar 7400 and the CMOS 4000 families of digital logic gates such as 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx, 74ACTxx etc, with each one having its own distinct advantages and disadvantages compared to the other. The exact switching voltage required to produce either a logic “0” or a logic “1” depends upon the specific logic group or family.

However, when using a standard +5 volt supply any TTL voltage input between 2.0v and 5v is considered to be a logic “1” or “HIGH” while any voltage input below 0.8v is recognised as a logic “0” or “LOW”. The voltage region in between these two voltage levels either as an input or as an output is called the Indeterminate Region and operating within this region may cause the logic gate to produce a false output.

The CMOS 4000 logic family uses different levels of voltages compared to the TTL types as they are designed using field effect transistors, or FET’s. In CMOS technology a logic “1” level operates between 3.0 and 18 volts and a logic “0” level is below 1.5 volts.

Then from the above observations, we can define the ideal Digital Logic Gate as one that has a “LOW” level logic “0” of 0 volts (ground) and a “HIGH” level logic “1” of +5 volts and this can be demonstrated as:

Ideal Digital Logic Gate Voltage Levels

Where the opening or closing of the switch produces either a logic level “1” or a logic level “0” with the resistor R being known as a “pull-up” resistor.

Digital Logic Noise

However, between these defined HIGH and LOW values lies what is generally called a “no-man’s land” (the blue area’s above) and if we apply a signal voltage of a value within this no-man’s land area we do not know whether the logic gate will respond to it as a level “0” or as a level “1”, and the output will become unpredictable.

Noise is the name given to a random and unwanted voltage that is induced into electronic circuits by external interference, such as from nearby switches, power supply fluctuations or from wires and other conductors that pick-up stray electromagnetic radiation. Then in order for a logic gate not to be influence by noise in must have a certain amount of noise margin or noise immunity.

Digital Logic Gate Noise Immunity

In the example above, the noise signal is superimposed onto the Vcc supply voltage and as long as it stays above the minimum level (Von-min) the input an corresponding output of the logic gate are unaffected. But when the noise level becomes large enough and a noise spike causes the HIGH voltage level to drop below this minimum level, the logic gate may interpret this spike as a LOW level input and switch the output accordingly producing a false output switching. Then in order for the logic gate not to be affected by noise it must be able to tolerate a certain amount of unwanted noise on its input without changing the state of its output.

Simple Basic Digital Logic Gates

Simple digital logic gates can be made by combining transistors, diodes and resistors with a simple example of a Diode-Resistor Logic (DRL) AND gate and a Diode-Transistor Logic (DTL) NAND gate given below.

Diode-Resistor Circuit	Diode-Transistor circuit
2-input AND Gate	2-input NAND Gate

The simple 2-input Diode-Resistor AND gate can be converted into a NAND gate by the addition of a single transistor inverting (NOT) stage. Using discrete components such as diodes, resistors and transistors to make digital logic gate circuits are not used in practical commercially available logic IC’s as these circuits suffer from propagation delay or gate delay and also power loss due to the pull-up resistors.

Another disadvantage of diode-resistor logic is that there is no “Fan-out” facility which is the ability of a single output to drive many inputs of the next stages. Also this type of design does not turn fully “OFF” as a Logic “0” produces an output voltage of 0.6v (diode voltage drop), so the following TTL and CMOS circuit designs are used instead.

Basic TTL Logic Gates

The simple Diode-Resistor AND gate above uses separate diodes for its inputs, one for each input. As a transistor is made up off two diode circuits connected together representing an NPN or a PNP device, the input diodes of the DTL circuit can be replaced by one single NPN transistor with multiple emitter inputs as shown.

As the NAND gate contains a single stage inverting NPN transistor circuit (TR₂) an output logic level “1” at Q is only present when both the emitters of TR₁ are connected to logic level “0” or ground allowing base current to pass through the PN junctions of the emitter and not the collector. The multiple emitters of TR₁ are connected as inputs thus producing a NAND gate function.

In standard TTL logic gates, the transistors operate either completely in the “cut off” region, or else completely in the saturated region, Transistor as a Switch type operation.

Emitter-Coupled Digital Logic Gate

Emitter Coupled Logic or ECL is another type of digital logic gate that uses bipolar transistor logic where the transistors are not operated in the saturation region, as they are with the standard TTL digital logic gate. Instead the input and output circuits are push-pull connected transistors with the supply voltage negative with respect to ground.

This has the effect of increasing the speed of operation of the emitter coupled logic gates up to the Gigahertz range compared with the standard TTL types, but noise has a greater effect in ECL logic, because the unsaturated transistors operate within their active region and amplify as well as switch signals.

The “74” Sub-families of Integrated Circuits

With improvements in the circuit design to take account of propagation delays, current consumption, fan-in and fan-out requirements etc, this type of TTL bipolar transistor technology forms the basis of the prefixed “74” family of digital logic IC’s, such as the “7400” Quad 2-input AND gate, or the “7402” Quad 2-input OR gate, etc.

Sub-families of the 74xx series IC’s are available relating to the different technologies used to fabricate the gates and they are denoted by the letters in between the 74 designation and the device number. There are a number of TTL sub-families available that provide a wide range of switching speeds and power consumption such as the 74L00 or 74ALS00 AND gate, were the “L” stands for “Low-power TTL” and the “ALS” stands for “Advanced Low-power Schottky TTL” and these are listed below.

• 74xx or 74Nxx: Standard TTL – These devices are the original TTL family of logic gates introduced in the early 70’s. They have a propagation delay of about 10ns and a power consumption of about 10mW.
• 74Lxx: Low Power TTL – Power consumption was improved over standard types by increasing the number of internal resistances but at the cost of a reduction in switching speed.
• 74Hxx: High Speed TTL – Switching speed was improved by reducing the number of internal resistances. This also increased the power consumption.
• 74Sxx: Schottky TTL – Schottky technology is used to improve input impedance, switching speed and power consumption (2mW) compared to the 74Lxx and 74Hxx types.
• 74LSxx: Low Power Schottky TTL – Same as 74Sxx types but with increased internal resistances to improve power consumption.
• 74ASxx: Advanced Schottky TTL – Improved design over 74Sxx Schottky types optimised to increase switching speed at the expense of power consumption of about 22mW.
• 74ALSxx: Advanced Low Power Schottky TTL – Lower power consumption of about 1mW and higher switching speed of about 4nS compared to 74LSxx types.
• 74HCxx: High Speed CMOS – CMOS technology and transistors to reduce power consumption of less than 1uA with CMOS compatible inputs.
• 74HCTxx: High Speed CMOS – CMOS technology and transistors to reduce power consumption of less than 1uA but has increased propagation delay of about 16nS due to the TTL compatible inputs.

Basic CMOS Digital Logic Gate

One of the main disadvantages with the TTL digital logic gate series is that the logic gates are based on bipolar transistor logic technology and as transistors are current operated devices, they consume large amounts of power from a fixed +5 volt power supply.

Also, TTL bipolar transistor gates have a limited operating speed when switching from an “OFF” state to an “ON” state and vice-versa called the “gate” or “propagation delay”. To overcome these limitations complementary MOS called “CMOS” logic gates using “Field Effect Transistors” or FET’s were developed.

As these gates use both P-channel and N-channel MOSFET’s as their input device, at quiescent conditions with no switching, the power consumption of CMOS gates is almost zero, (1 to 2uA) making them ideal for use in low-power battery circuits and with switching speeds upwards of 100MHz for use in high frequency timing and computer circuits.

This CMOS gate example contains 3 N-channel MOSFET’s, one for each input FET₁ and FET₂ and one for the output FET₃. When both the inputs A and B are at logic level “0”, FET₁ and FET₂ are both switched “OFF” giving an output logic “1” from the source of FET₃.

When one or both of the inputs are at logic level “1” current flows through the corresponding FET giving an output state atQ equivalent to logic “0”, thus producing a NAND gate function.

Improvements in the circuit design with regards to switching speed, low power consumption and improved propagation delays has resulted in the standard CMOS 4000 “CD” family of logic IC’s being developed that complement the TTL range.

As with the standard TTL digital logic gates, all the major digital logic gates and devices are available in the CMOS package such as the CD4011, a Quad 2-input NAND gate, or the CD4001, a Quad 2-input NOR gate along with all their sub-families.

Like TTL logic, complementary MOS (CMOS) circuits take advantage of the fact that both N-channel and P-channel devices can be fabricated together on the same substrate material to form various logic functions.

One of the main disadvantage with the CMOS range of IC’s compared to their equivalent TTL types is that they are easily damaged by static electricity so extra care must be taken when handling these devices. Also unlike TTL logic gates that operate on single +5V voltages for both their input and output levels, CMOS digital logic gates operate on a single supply voltage of between +3 and +18 volts.

In the next tutorial about Digital Logic Gates, we will look at the digital Logic AND Gate function as used in both TTL and CMOS logic circuits as well as its Boolean Algebra definition and truth tables.

XNOR Gates

XNOR gates have two bits of input and a single bit of output.

The output of XNOR gate is the negation of XOR and has logic '1' when both inputs are the same.

If you look carefully at the drawing of the gate, there is a second arc behind the first one near the inputs. Since this second arc is hard to see, it's usually a good idea to write the word "XNOR" inside the gate.

The truth table defines the behavior of this gate.

The function implmented by XNOR gates has interesting properties:

The function is symmetric. Thus, x XNOR y == y XNOR x. This can be verified by using truth tables.

The function is associative. Thus, (x XNOR y) XNOR z == x XNOR (y XNOR z). This can be verified by using truth tables.

Because of these properties, it's easy to define XNORn, which is an n-input XNOR gate.

XNORn(x1, x2,...,xn) = x1 XNOR x2 XNOR ... XNOR xn

That is, an XNOR gate with n-inputs is the XNOR of all the bits. This is not ambiguous because the XNOR function is associative (all parenthesization of this expression are equivalent).

(Error-checkers! You may wish to verify this, and email me if this is incorrect!).

XOR Gates

XOR gates have two bits of input and a single bit of output. The output of XOR gate is logic '1' only if the inputs have opposite values. That is, when one input has value logic '0', and the other has value logic '1'. Otherwise, the output is logic '0'.

This is called Exclusive-OR. The definition of OR is inclusive-or, where the output is logic '1' if either input is logic '1', or if both inputs are logic '1'.

XOR can be defined using AND, OR, and NOT.

x XOR y == ( x AND (NOT y) ) OR ( (NOT x) AND y ) 

Here's a diagram of the XOR2 gate.

If you look carefully at the drawing of the gate, there is a second arc behind the first one near the inputs. Since this second arc is hard to see, it's usually a good idea to write the word "XOR" inside the gate.

The truth table defines the behavior of this gate.

The function implmented by XOR gates has interesting properties:

The function is symmetric. Thus, x (+) y == y (+) x. This can be verified by using truth tables. (We use (+) to denote logical XOR--ideally, we'd draw it with a + sign inside a circle, but HTML doesn't seem to have a symbol for this).

The function is associative. Thus, [ x (+) y ] (+) z == x (+) [ y (+) z ]. This can be verified by using truth tables.

Because of these properties, it's easy to define XORn, which is an n-input XOR gate.

XORn(x1, x2,...,xn) = x1 (+) x2 (+) ... (+) xn

That is, an XOR gate with n-inputs is the XOR of all the bits. This is not ambiguous because the XOR function is associative (all parenthesization of this expression are equivalent).

NOR Gates

NOR gates have two bits of input and a single bit of output. The output of NOR gate is the negation of OR gate.

The truth table defines the behavior of this gate.

The function implmented by NOR gates has interesting properties:

The function is symmetric. Thus, x NOR y == y NOR x. This can be verified by using truth tables.
The function is not associative. This can be verified by using truth tables.
Because of these properties, NORk is defined from ORk and NOT built from NOR gates.

NAND Gates

NAND gates have two bits of input and a single bit of output.
Since NAND is not associative, the definition is based on AND.

In particular

NANDk(x1, x2,...,xn) = NOT( ANDk(x1, x2,...,xn) )

Thus, NANDk is the negation of ANDk.

The truth table defines the behavior of this gate. It's the negation of AND.

The function implemented by NAND gates has interesting properties:

The function is symmetric. Thus, x NAND y == y NAND x. This can be verified by using truth tables.

The function is not associative. This can be verified by using truth tables.

Because of these properties, NANDk is defined from ANDk, and not built from NAND gates.

OR Gates

OR gates have two bits of input and a single bit of output.

The output of OR gate is logic '0' only if both inputs are logic '0'. Otherwise, the output is logic '1'.

The truth table defines the behavior of this gate.

The function implemented by OR gates has interesting properties:

The function is symmetric. Thus, x + y == y + x. This can be verified by using truth tables. We use "+" to represent OR.

The function is associative. Thus, (x + y) + z == x + (y + z). This can be verified by using truth tables.
Because of these properties, it's easy to define an n-input OR gate.

ORn(x1, x2,...,xn) = x1 + x2 + ... + xn
That is, an OR gate with n-inputs is the OR of all the bits. This is not ambiguous because the OR function is associative (all parenthesization of this expression are equivalent).

AND Gates

An AND gate have two bits of input and a single bit of output.
The output of AND gate is logic '1' only if both inputs are at logic '1'. Otherwise, the output is logic '0'.

The truth table defines the behavior of this gate.

The function implmented by AND2 gates has interesting properties:

The function is symmetric. Thus, x * y == y * x. This can be verified by using truth tables. We use * to represent AND.

The function is associative. Thus, (x * y) * z == x * (y * z). This can be verified by using truth tables.
Because of these properties, it's easy to define an n-input AND gate.

ANDn(x1, x2,...,xn) = x1 * x2 * ... * xn

That is, an AND gate with n-inputs is the AND of all the bits. This is not ambiguous because the AND function is associative (all parenthesization of this expression are equivalent).

VHDL code for AND gate

Logic NOT Gate

Logic Gates
NOT	AND	OR	NAND	NOR	XOR	XNOR

The Logic “NOT” Gate

Logic NOT Gate Definition

The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes referred to as an Inverting Buffer or simply a Digital Inverter. It is a single input device which has an output level that is normally at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”, in other words it “inverts” (complements) its input signal. The output from a NOT gate only returns “HIGH” again when its input is at logic level “0” giving us the Boolean expression of:  A = Q.

Then we can define the operation of a single input Digital Logic NOT Gate as being:

“If A is NOT true, then Q is true”

Transistor NOT Gate

A simple 2-input logic NOT gate can be constructed using a RTL Resistor-transistor switches as shown below with the input connected directly to the transistor base. The transistor must be saturated “ON” for an inverted output “OFF” at Q.

The Logic NOT Gate Truth Table

Symbol	Truth Table
Inverter or NOT Gate	A	Q
	0	1
	1	0
Boolean Expression Q = not A or A	Read as inverse of A gives Q

Logic NOT gates provide the complement of their input signal and are so called because when their input signal is “HIGH” their output state will NOT be “HIGH”. Likewise, when their input signal is “LOW” their output state will NOT be “LOW”. As they are single input devices, logic NOT gates are not normally classed as “decision” making devices or even as a gate, such as the AND or OR gates which have two or more logic inputs. Commercial available NOT gates IC’s are available in either 4 or 6 individual gates within a single IC package.

The “bubble” (o) present at the end of the NOT gate symbol above denotes a signal inversion (complementation) of the output signal. But this bubble can also be present at the gates input to indicate an active-LOW input. This inversion of the input signal is not restricted to the NOT gate only but can be used on any digital circuit or gate as shown with the operation of inversion being exactly the same whether on the input or output terminal. The easiest way is to think of the bubble as simply an inverter.

Signal Inversion using Active-low input Bubble

Bubble Notation for Input Inversion

NAND and NOR Gate Equivalents

An Inverter or logic NOT gate can also be made using standard NAND and NOR gates by connecting together ALL their inputs to a common input signal for example.

A very simple inverter can also be made using just a single stage transistor switching circuit as shown. When the transistors base input at “A” is high, the transistor conducts and collector current flows producing a voltage drop across the resistor R thereby connecting the output point at “Q” to ground thus resulting in a zero voltage output at “Q”.

Likewise, when the transistors base input at “A” is low (0v), the transistor now switches “OFF” and no collector current flows through the resistor resulting in an output voltage at “Q” high at a value near to +Vcc.

Then, with an input voltage at “A” HIGH, the output at “Q” will be LOW and an input voltage at “A” LOW the resulting output voltage at “Q” is HIGH producing the complement or inversion of the input signal.

Hex Schmitt Inverters

A standard Inverter or Logic NOT Gate, is usually made up from transistor switching circuits that do not switch from one state to the next instantly, there will always be some delay in the switching action.

Also as a transistor is a basic current amplifier, it can also operate in a linear mode and any small variation to its input level will cause a variation to its output level or may even switch “ON” and “OFF” several times if there is any noise present in the circuit. One way to overcome these problems is to use a Schmitt Inverter or Hex Inverter.

We know from the previous pages that all digital gates use only two logic voltage states and that these are generally referred to as Logic “1” and Logic “0” any TTL voltage input between 2.0v and 5v is recognised as a logic “1” and any voltage input below 0.8v is recognised as a logic “0” respectively.

A Schmitt Inverter is designed to operate or switch state when its input signal goes above an “Upper Threshold Voltage” or UTV limit in which case the output changes and goes “LOW”, and will remain in that state until the input signal falls below the “Lower Threshold Voltage” or LTV level in which case the output signal goes “HIGH”. In other words a Schmitt Inverter has some form of Hysteresis built into its switching circuit.

This switching action between an upper and lower threshold limit provides a much cleaner and faster “ON/OFF” switching output signal and makes the Schmitt inverter ideal for switching any slow-rising or slow-falling input signal and as such we can use a Schmitt trigger to convert these analogue signals into digital signals as shown.

Schmitt Inverter

A very useful application of Schmitt inverters is when they are used as oscillators or sine-to-square wave converters for use as square wave clock signals.

Schmitt NOT Gate Inverter Oscillator

The first circuit shows a very simple low power RC type oscillator using a Schmitt inverter to generate a square wave output waveform. Initially the capacitor C is fully discharged so the input to the inverter is “LOW” resulting in an inverted output which is “HIGH”. As the output from the inverter is fed back to its input and the capacitor via the resistor R the capacitor begins to charge up.

When the capacitors charging voltage reaches the upper threshold limit of the inverter, the inverter changes state, the output becomes “LOW” and the capacitor begins to discharge through the resistor until it reaches the lower threshold level were the inverter changes state again. This switching back and forth by the inverter produces a square wave output signal with a 33% duty cycle and whose frequency is given as: ƒ = 680/RC.

The second circuit converts a sine wave input (or any oscillating input for that matter) into a square wave output. The input to the inverter is connected to the junction of the potential divider network which is used to set the quiescent point of the circuit. The input capacitor blocks any DC component present in the input signal only allowing the sine wave signal to pass.

As this signal passes the upper and lower threshold points of the inverter the output also changes from “HIGH” to “LOW” and so on producing a square wave output waveform. This circuit produces an output pulse on the positive rising edge of the input waveform, but by connecting a second Schmitt inverter to the output of the first, the basic circuit can be modified to produce an output pulse on the negative falling edge of the input signal.

Commonly available logic NOT gate and Inverter IC’s include:

TTL Logic NOT Gates

• 74LS04 Hex Inverting NOT Gate
• 74LS14 Hex Schmitt Inverting NOT Gate
• 74LS1004 Hex Inverting Drivers

CMOS Logic NOT Gates

• CD4009 Hex Inverting NOT Gate
• CD4069 Hex Inverting NOT Gate

7404 NOT Gate or Inverter