VHDL Functions

I think all of the Designer wanted the Code simple and understandable. In simulation functions can be used to accomplish all kinds of things but For synthesis we must be more careful. Functions can be useful to model a component or a type conversion.

Warning, though!!! You must THINK HARDWARE!!!

Many functions have been defined in the IEEE libraries, e.g. rising_edge(CLK)

Function Properties :

• Function parameters can only be inputs.
• Functions can only return one value, specified by “return”.
• Statements inside the function are sequential except signal assignment and wait.
• No new signals can be declared, but variables can be.
• A function may declare local variables. These do not retain their values between successive calls, but are re-initialized each time.
• A function can be called as an expression, in either a concurrent or sequential statement
• Functions can be included either explicitly or through the use of packages.

Syntax:

function function_name (parameter_list) return type is
    declarations
begin
    sequential statements
end function_name;

Example:
entity full_add is
port(
         a, b, carry_in: in bit;
         sum, carry_out: out bit);
end full_add;

architecture full_add_arch of full_add is

function carry (a, b, c: in bit) return bit is
  begin
        return ((a and b) or (a and c) or (b and c));
end majority;

begin
       sum <= a xor b xor carry_in;
       carry_out <= carry(a, b, carry_in);
end full_add_arch;