DDR4 is the next evolution in DRAM, bringing even higher performance and more robust control features while improving energy economy for enterprise, micro-server, tablet, and ultrathin client applications. The following table compares some of the key feature differences between DDR3 and DDR4.
Feature/Option | DDR3 | DDR4 | DDR4 Advantage |
Voltage (core and I/O) | 1.5V | 1.2V | Reduces memory power demand |
VREF inputs | 2 – DQs and CMD/ADDR | 1 – CMD/ADDR | VREFDQ now internal |
Low voltage standard | Yes (DDR3L at 1.35V) | Anticipated (likely 1.05V) | Memory power reductions |
Data rate (Mb/s) | 800, 1066, 1333, 1600, 1866, 2133 | 1600, 1866, 2133, 2400, 2667, 3200 | Migration to higher‐speed I/O |
Densities | 512Mb–8Gb | 2Gb–16Gb | Better enablement for large-capacity memory subsystems |
Internal banks | 8 | 16 | More banks |
Bank groups (BG) | 0 | 4 | Faster burst accesses |
tCK – DLL enabled | 300 MHz to 800 MHz | 667 MHz to 1.6 GHz | Higher data rates |
tCK – DLL disabled | 10 MHz to 125 MHz (optional) | Undefined to 125 MHz | DLL-off now fully supported |
Read latency | AL + CL | AL + CL | Expanded values |
Write latency | AL + CWL | AL + CWL | Expanded values |
DQ driver (ALT) | 40Ω | 48Ω | Optimized for PtP (point-to-point) applications |
DQ bus | SSTL15 | POD12 | Mitigate I/O noise and power |
RTT values (in Ω) | 120, 60, 40, 30, 20 | 240, 120, 80, 60, 48, 40, 34 | Support higher data rates |
RTT not allowed | READ bursts | Disables during READ bursts | Ease-of-use |
ODT modes | Nominal, dynamic | Nominal, dynamic, park | Additional control mode; supports OTF value change |
ODT control | ODT signaling required | ODT signaling not required | Ease of ODT control, allows non-ODT routing on PtP applications |
Multipurpose register (MPR) | Four registers – 1 defined, 3 RFU | Four registers – 3 defined, 1 RFU | Provides additional specialty readout |
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