VLSI Project And Training At Ahmedabad

Chip design in India has been identified as a prominent industry to support the already achieved development in IT field. With growing design houses day by day, a large pool of highly skilled individuals is needed to meet this demand. But, a potential gap was evident in the expectations of the industry and the output from academic institutions.

Realizing this need for trained manpower, we had launched a Certificate in Digital VLSI Design with emphasis on Digital CMOS circuit design, VLSI design flows, verification and testing including a minor and a major project. This course will be effective in providing potential engineers with exposure to both front-end and back-end processes in VLSI Design.

At Ahmedabad few institutions are offering courses in VLSI Front-end designing with following course contents.

Advance Digital Design

• Digital Logic Fundamentals
• Combinational logic design
• Sequential logic design
• Programmable logic
• State machines

VHDL

• VHDL Overview and Concepts
• Levels of Abstraction
• Entity, Architecture
• Data Types and declaration
• Enumerated Data Types
• Relational, Logical, Arithmetic Operators
• Signal and Variables, Constants
• Process Statement
• Concurrent Statements
• When-else, With-select
• Sequential Statement
• If-then-else, Case
• Slicing and Concatenation
• Loop Statements
• Delta Delay Concept
• Arrays, Memory Modeling, FSM
• Writing Procedures
• Writing Functions
• Behavioral / RTL Coding
• Operator Overloading
• Structural Coding
• Component declarations and installations
• Generate Statement
• Configuration Block
• Libraries, Standard packages
• Local and Global Declarations
• Package, Package body
• Writing Test Benches
• Assertion based verification
• Files read and write operations
• Code for complex FPGA and ASICs
• Generics and Generic maps

VERILOG

• Language introduction
• Levels of abstraction
• Module, Ports types and declarations
• Registers and nets, Arrays
• Identifiers, Parameters
• Relational, Arithmetic, Logical, Bit-wise shift Operators
• Writing expressions
• Behavioral Modeling
• Structural Coding
• Continuous Assignments
• Procedural Statements
• Always, Initial Blocks, begin ebd, fork join
• Blocking and Non-blocking statements
• Operation Control Statements
• If, case
• Loops: while, for-loop, for-each, repeat
• Combination and sequential circuit designs
• Memory modeling,, state machines
• CMOS gate modeling
• Writing Tasks
• Writing Functions
• Compiler directives
• Conditional Compilation
• System Tasks
• Gate level primitives
• User defined primitives
• Delays, Specify block
• Testbenchs, modeling, timing checks
• Assertion based verification
• Code for synthesis
• Advanced topics
• Writing reusable code

FPGA Flow

• Re-configurable Devices, FPGA’s/CPLD’s
• Architectures of XILINX, ALTERA Devices
• Designing with FPGAs
• FPGA’s and its Design Flows
• Architecture based coding
• Efficient resource utilization
• Constrains based synthesis
• False paths and multi cycle paths
• UCF file creation
• Timing analysis/Floor Planning
• Place and route/RPM
• Back annotation, Gate level simulation, SDF Format
• DSP on FPGA
• Writing Scripts
• Hands on experience with industry Standard Tools
• Synthesis Concepts
• HDL Implementation design cycle
• ASIC Implementation design cycle
• Sequential design optimization
• Synchronous Design
• Asynchronous design
• Guidelines for reset
• Synchronous and Asynchronous reset
• Guidelines for clock structures
• Gated clocks
• VHDL synthesis
• Synthesizable and Non-synthesizable VHDL constructs
• Verilog Synthesis
• Synthesizable and Non-synthesizable VHDL constructs

Timing Analysis

• Static timing analysis
• Dynamic timing analysis
• Setup time
• Hold time
• Setup and Hold checks
• Setup and Hold timing analysis
• Timing paths
• Clock skew

SystemVerilog

• SystemVerilog data types
• Nets and veriables
• Modules and processes
• Interfaces
• SystemVerilog assertions
• Module based SystemVerilog Verification
• Introduction to SystemVerilog classes
• Randomization in SystemVerilog
• Functionsla coverage

 
Verification concepts. Testbench environment development using UVM/OVM methodologies.

Total course duration including major project: 6 months

Course Highlights :

• Advanced Digital Design And Verilog Coding Techniques
• Advanced Verification Techniques
• Synthesis and Static Timing Analysis
• Floor Planning, Placement And Routing
• Interview Preparation and Mock Interviews

For more detail please write to

info@vlsiencyclopedia.com 
Contact : +91-9824245665