XNOR Gates

XNOR gates have two bits of input and a single bit of output.

The output of XNOR gate is the negation of XOR and has logic '1' when both inputs are the same.

If you look carefully at the drawing of the gate, there is a second arc behind the first one near the inputs. Since this second arc is hard to see, it's usually a good idea to write the word "XNOR" inside the gate.

The truth table defines the behavior of this gate.

The function implmented by XNOR gates has interesting properties:

The function is symmetric. Thus, x XNOR y == y XNOR x. This can be verified by using truth tables.

The function is associative. Thus, (x XNOR y) XNOR z == x XNOR (y XNOR z). This can be verified by using truth tables.

Because of these properties, it's easy to define XNORn, which is an n-input XNOR gate.

XNORn(x1, x2,...,xn) = x1 XNOR x2 XNOR ... XNOR xn

That is, an XNOR gate with n-inputs is the XNOR of all the bits. This is not ambiguous because the XNOR function is associative (all parenthesization of this expression are equivalent).

(Error-checkers! You may wish to verify this, and email me if this is incorrect!).

XOR Gates

XOR gates have two bits of input and a single bit of output. The output of XOR gate is logic '1' only if the inputs have opposite values. That is, when one input has value logic '0', and the other has value logic '1'. Otherwise, the output is logic '0'.

This is called Exclusive-OR. The definition of OR is inclusive-or, where the output is logic '1' if either input is logic '1', or if both inputs are logic '1'.

XOR can be defined using AND, OR, and NOT.

x XOR y == ( x AND (NOT y) ) OR ( (NOT x) AND y ) 

Here's a diagram of the XOR2 gate.

If you look carefully at the drawing of the gate, there is a second arc behind the first one near the inputs. Since this second arc is hard to see, it's usually a good idea to write the word "XOR" inside the gate.

The truth table defines the behavior of this gate.

The function implmented by XOR gates has interesting properties:

The function is symmetric. Thus, x (+) y == y (+) x. This can be verified by using truth tables. (We use (+) to denote logical XOR--ideally, we'd draw it with a + sign inside a circle, but HTML doesn't seem to have a symbol for this).

The function is associative. Thus, [ x (+) y ] (+) z == x (+) [ y (+) z ]. This can be verified by using truth tables.

Because of these properties, it's easy to define XORn, which is an n-input XOR gate.

XORn(x1, x2,...,xn) = x1 (+) x2 (+) ... (+) xn

That is, an XOR gate with n-inputs is the XOR of all the bits. This is not ambiguous because the XOR function is associative (all parenthesization of this expression are equivalent).

NOR Gates

NOR gates have two bits of input and a single bit of output. The output of NOR gate is the negation of OR gate.

The truth table defines the behavior of this gate.

The function implmented by NOR gates has interesting properties:

The function is symmetric. Thus, x NOR y == y NOR x. This can be verified by using truth tables.
The function is not associative. This can be verified by using truth tables.
Because of these properties, NORk is defined from ORk and NOT built from NOR gates.

NAND Gates

NAND gates have two bits of input and a single bit of output.
Since NAND is not associative, the definition is based on AND.

In particular

NANDk(x1, x2,...,xn) = NOT( ANDk(x1, x2,...,xn) )

Thus, NANDk is the negation of ANDk.

The truth table defines the behavior of this gate. It's the negation of AND.

The function implemented by NAND gates has interesting properties:

The function is symmetric. Thus, x NAND y == y NAND x. This can be verified by using truth tables.

The function is not associative. This can be verified by using truth tables.

Because of these properties, NANDk is defined from ANDk, and not built from NAND gates.

OR Gates

OR gates have two bits of input and a single bit of output.

The output of OR gate is logic '0' only if both inputs are logic '0'. Otherwise, the output is logic '1'.

The truth table defines the behavior of this gate.

The function implemented by OR gates has interesting properties:

The function is symmetric. Thus, x + y == y + x. This can be verified by using truth tables. We use "+" to represent OR.

The function is associative. Thus, (x + y) + z == x + (y + z). This can be verified by using truth tables.
Because of these properties, it's easy to define an n-input OR gate.

ORn(x1, x2,...,xn) = x1 + x2 + ... + xn
That is, an OR gate with n-inputs is the OR of all the bits. This is not ambiguous because the OR function is associative (all parenthesization of this expression are equivalent).

AND Gates

An AND gate have two bits of input and a single bit of output.
The output of AND gate is logic '1' only if both inputs are at logic '1'. Otherwise, the output is logic '0'.

The truth table defines the behavior of this gate.

The function implmented by AND2 gates has interesting properties:

The function is symmetric. Thus, x * y == y * x. This can be verified by using truth tables. We use * to represent AND.

The function is associative. Thus, (x * y) * z == x * (y * z). This can be verified by using truth tables.
Because of these properties, it's easy to define an n-input AND gate.

ANDn(x1, x2,...,xn) = x1 * x2 * ... * xn

That is, an AND gate with n-inputs is the AND of all the bits. This is not ambiguous because the AND function is associative (all parenthesization of this expression are equivalent).

VHDL code for AND gate

Logic NOT Gate

Logic Gates
NOT	AND	OR	NAND	NOR	XOR	XNOR

The Logic “NOT” Gate

Logic NOT Gate Definition

The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes referred to as an Inverting Buffer or simply a Digital Inverter. It is a single input device which has an output level that is normally at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”, in other words it “inverts” (complements) its input signal. The output from a NOT gate only returns “HIGH” again when its input is at logic level “0” giving us the Boolean expression of:  A = Q.

Then we can define the operation of a single input Digital Logic NOT Gate as being:

“If A is NOT true, then Q is true”

Transistor NOT Gate

A simple 2-input logic NOT gate can be constructed using a RTL Resistor-transistor switches as shown below with the input connected directly to the transistor base. The transistor must be saturated “ON” for an inverted output “OFF” at Q.

The Logic NOT Gate Truth Table

Symbol	Truth Table
Inverter or NOT Gate	A	Q
	0	1
	1	0
Boolean Expression Q = not A or A	Read as inverse of A gives Q

Logic NOT gates provide the complement of their input signal and are so called because when their input signal is “HIGH” their output state will NOT be “HIGH”. Likewise, when their input signal is “LOW” their output state will NOT be “LOW”. As they are single input devices, logic NOT gates are not normally classed as “decision” making devices or even as a gate, such as the AND or OR gates which have two or more logic inputs. Commercial available NOT gates IC’s are available in either 4 or 6 individual gates within a single IC package.

The “bubble” (o) present at the end of the NOT gate symbol above denotes a signal inversion (complementation) of the output signal. But this bubble can also be present at the gates input to indicate an active-LOW input. This inversion of the input signal is not restricted to the NOT gate only but can be used on any digital circuit or gate as shown with the operation of inversion being exactly the same whether on the input or output terminal. The easiest way is to think of the bubble as simply an inverter.

Signal Inversion using Active-low input Bubble

Bubble Notation for Input Inversion

NAND and NOR Gate Equivalents

An Inverter or logic NOT gate can also be made using standard NAND and NOR gates by connecting together ALL their inputs to a common input signal for example.

A very simple inverter can also be made using just a single stage transistor switching circuit as shown. When the transistors base input at “A” is high, the transistor conducts and collector current flows producing a voltage drop across the resistor R thereby connecting the output point at “Q” to ground thus resulting in a zero voltage output at “Q”.

Likewise, when the transistors base input at “A” is low (0v), the transistor now switches “OFF” and no collector current flows through the resistor resulting in an output voltage at “Q” high at a value near to +Vcc.

Then, with an input voltage at “A” HIGH, the output at “Q” will be LOW and an input voltage at “A” LOW the resulting output voltage at “Q” is HIGH producing the complement or inversion of the input signal.

Hex Schmitt Inverters

A standard Inverter or Logic NOT Gate, is usually made up from transistor switching circuits that do not switch from one state to the next instantly, there will always be some delay in the switching action.

Also as a transistor is a basic current amplifier, it can also operate in a linear mode and any small variation to its input level will cause a variation to its output level or may even switch “ON” and “OFF” several times if there is any noise present in the circuit. One way to overcome these problems is to use a Schmitt Inverter or Hex Inverter.

We know from the previous pages that all digital gates use only two logic voltage states and that these are generally referred to as Logic “1” and Logic “0” any TTL voltage input between 2.0v and 5v is recognised as a logic “1” and any voltage input below 0.8v is recognised as a logic “0” respectively.

A Schmitt Inverter is designed to operate or switch state when its input signal goes above an “Upper Threshold Voltage” or UTV limit in which case the output changes and goes “LOW”, and will remain in that state until the input signal falls below the “Lower Threshold Voltage” or LTV level in which case the output signal goes “HIGH”. In other words a Schmitt Inverter has some form of Hysteresis built into its switching circuit.

This switching action between an upper and lower threshold limit provides a much cleaner and faster “ON/OFF” switching output signal and makes the Schmitt inverter ideal for switching any slow-rising or slow-falling input signal and as such we can use a Schmitt trigger to convert these analogue signals into digital signals as shown.

Schmitt Inverter

A very useful application of Schmitt inverters is when they are used as oscillators or sine-to-square wave converters for use as square wave clock signals.

Schmitt NOT Gate Inverter Oscillator

The first circuit shows a very simple low power RC type oscillator using a Schmitt inverter to generate a square wave output waveform. Initially the capacitor C is fully discharged so the input to the inverter is “LOW” resulting in an inverted output which is “HIGH”. As the output from the inverter is fed back to its input and the capacitor via the resistor R the capacitor begins to charge up.

When the capacitors charging voltage reaches the upper threshold limit of the inverter, the inverter changes state, the output becomes “LOW” and the capacitor begins to discharge through the resistor until it reaches the lower threshold level were the inverter changes state again. This switching back and forth by the inverter produces a square wave output signal with a 33% duty cycle and whose frequency is given as: ƒ = 680/RC.

The second circuit converts a sine wave input (or any oscillating input for that matter) into a square wave output. The input to the inverter is connected to the junction of the potential divider network which is used to set the quiescent point of the circuit. The input capacitor blocks any DC component present in the input signal only allowing the sine wave signal to pass.

As this signal passes the upper and lower threshold points of the inverter the output also changes from “HIGH” to “LOW” and so on producing a square wave output waveform. This circuit produces an output pulse on the positive rising edge of the input waveform, but by connecting a second Schmitt inverter to the output of the first, the basic circuit can be modified to produce an output pulse on the negative falling edge of the input signal.

Commonly available logic NOT gate and Inverter IC’s include:

TTL Logic NOT Gates

• 74LS04 Hex Inverting NOT Gate
• 74LS14 Hex Schmitt Inverting NOT Gate
• 74LS1004 Hex Inverting Drivers

CMOS Logic NOT Gates

• CD4009 Hex Inverting NOT Gate
• CD4069 Hex Inverting NOT Gate

7404 NOT Gate or Inverter