Delays

Formal Definition

Delays specify a time in which assigned values propagate through nets or from inputs to outputs of gates.

Simplified Syntax

#value

#(value)

#(value, value)

#(value, value, value)

Description

Delays specify how values propagate through nets or gates.

The net delay declaration specifies a time needed to propagate values from drivers through the net. It can be used in continuous assignments (Example 1) and net declarations (Example 2).

The gate delay declaration specifies a time needed to propagate a signal change from the input of a gate input to its output. The gate delay declaration can be used in gate instantiations (Example 3).

The delays can be also used for delay control in procedural statements (Example 4 - see Procedural timing control for more explanations).

The delays declaration can contain up to three values: rise, fall, and turn-off delays. The default delay is zero. If only one delay value is specified then it is used for all signal changes. If two delays are specified then the first delay specifies the rise delay and the second delay specifies the fall delay. If the signal changes to high-impedance (z) or to unknown (x) then the smaller value will be used. This means that if delays are specified as follows: #(4,3) then the second value (3) will be used for signal changes to z or x value.

If three values are given, then the first value specifies the rise delay, the second specifies the fall delay, and the third specifies turn-off delay. If the signal changes to unknown (x) value, then the smallest of these three values will be used.

Value changes		Delay used for propagation if:
From:	To:	1 delay specified	2 delays specified	3 delays specified
0	1	d1	d1	d1
0	x	d1	min(d1, d2)	min(d1, d2, d3)
0	z	d1	min(d1, d2)	d3
1	0	d1	d2	d2
1	x	d1	min(d1, d2)	min(d1, d2, d3)
1	z	d1	min(d1, d2)	d3
x	0	d1	d2	d2
x	1	d1	d1	d1
x	z	d1	min(d1, d2)	d3
z	0	d1	d2	d2
z	1	d1	d1	d1
z	x	D1	min(d1, d2)	min(d1, d2, d3)

Table 6 Rules for delays depending on number of specified values

Examples

Example 1

assign #5 out = in1 & in2;

All value changes on in1 or in2 signals will propagate to out port in 5 time units.

assign #(1,3) b = ~a;

All value changes on signal 'a' that cause signal 'b' to change its value to '1', will propagate through net 'b' in 1 time unit. If '~a' expression equals 0 then it will take 3 time units to propagate this value through net 'b'. If the result of '~a' expression is unknown (x) or high-impedance (z) value, then it will take 1 time unit (because 1 is less than 3 therefore this value will be used for propagating these value changes).

assign #(5,3,7) w_or = |bus;

If result of right-side expressions is 1 then 5 will be used as the delay.

If result of right-side expressions is 0 then 3 will be used as the delay.

If result of right-side expressions is high-impedance (z) then 7 will be used as the delay.

If result of right-side expressions is unknown (x) then 3 will be used as the delay (because this is the smallest of these three values).

Example 2

wire #(5) ready;
tri #(2,3) a;
wand #(3,2,1) signal_1;

Net ready has only one delay specified.

Net a has two delays specified.

Net signal_1 has three delays specified.

Example 3

and #1 and_gate (o, i1, i2);
or #(5,1) or_gate (o, i1, i2);
bufif1 #(3,4,5) buffer (o, i, c);

The and_gate has one delay specified.

The or_gate has two delays specified.

The buffer has three delays specified.

Example 4

reg r;
initial begin
  #10 r = 1'b1;
  r = #10 1'b0;
end

Important Notes

• If fewer than 3 delays are specified then the smallest value is used for the missing delay(s).

Conditional Operator

Formal Definition

The conditional operator selects an expression for evaluation depending on the value of condition.

Simplified Syntax

condition ? expression1 : expression2;

Description

If the condition is evaluated as false (or zero value) then expression2 is evaluated and used as a result of an entire expression. If condition is evaluated as true (or non-zero value) then expression1 is evaluated. In case condition is evaluated as x or z value, then both expresion1 and expression2 are evaluated, and the result is calculated bit by bit on the basis of the following table:

	0	1	x	z
0	0	x	x	x
1	x	1	x	x
x	x	x	x	x
z	x	x	x	x

Table 5 Results of bit by bit calculation.

If one of the expressions is of real type then the result of the whole expression should be 0 (zero). If expressions have different lengths, then length of an entire expression will be extended to the length of the longer expression. Trailing 0s will be added to the shorter expression.

The conditional operator can be nested (Example 3) and its behavior is identical with the case statement behavior.

Examples

Example 1

(a) ? 4'b110x : 4'b1000;

If 'a' has a non-zero value then the result of this expression is 4'b110x. If 'a' is 0, then the result of this expression is 4'b1000. If 'a' is x value then the result is 4'b1x0x (this is due to the fact that the result must be calculated bit by bit on the basis of the Table 1).

Example 2

assign data_out = (enable) ? data_reg : 8'bz;

The above example shows modeling tri-state buffers.

Example 3

reg [4:0] mux;
reg [1:0] addr;
mux = (addr == 2'b00) ? i0 :
  ((addr == 2'b01) ? i1 :
  ((addr == 2'b10) ? i2 :
  ((addr == 2'b11) ? i3 :
  4'bz)));
case (addr)
  2'b00: mux = i0;
  2'b01: mux = i1;
  2'b10: mux = i2;
  2'b11: mux = i3;
  default: mux = 4'bz;
endcase

Two different methods of modeling a multiplexer.

Important Notes

• Conditional operator can be used for tri-state buffer modeling.
• Conditional operator can be nested (its behavior is identical with the case statement behavior).

Compiler Directives

Formal Definition

Compiler directives are instructions affecting the compilation.

Simplified Syntax

`celldefine

  module_declaration

`endcelldefine

`default_nettype net_type_identifier

`define macro_name macro_text

`define macro_name(list_of_arguments) macro_text

`undef macro_name

`ifdef macro_name

  group_of_lines

`else

  group_of_lines

`endif

`include "filename"

`resetall

`timescale time_unit / time_precision

`unconnected_drive

  module_declaration

`nounconnected_drive

Description

All compiler directives are preceded by an accent grave (`) character. Compiler directives work from the point where they were used until the end of compilation or until a point where they are used again (even if the next usage occurs in another file).

`celldefine and `endcelldefine

These directives mark modules as cell modules (Example 1). They should be used in pairs outside the module definition.

`default_nettype

This directive sets net type used in implicit net declarations (Example 2). The default type is a wire. The `default_nettype directive should be used outside the module definition. The directive parameter can be one of following types:

wire, tri, tri0, tri1, wand, triand, wor, trior, trireg.

`define and `undef

These directives define and undefine text macros that can be used as a text substitution (Example 3). This is very useful in modeling because all changes can be applied in one place of the source code (in macro definition).

A macro can be defined with arguments, so every macro call can be followed by actual parameters.

The compiler recognizes a macro by its name preceded by accent grave (`) character.

`ifdef, `else, and `endif

These directives can be used to decide which lines of Verilog code should be included for the compilation (Example 4).

The `ifdef directive checks if a macro name that follows this directive is defined. If it is, then all lines between `ifdef and `else will be included. Otherwise, only lines between `elseand `endif will be compiled.

`include

The `include directive (Example 4) inserts the contents of a specified file into a file in which it was called. The file name should be given in quotation marks (") and it can be given using full or relative path.

`resetall

This compiler directive turns off all previously used compiler directives.

`timescale

This directive specifies time unit and time precision for simulation of modules that follow it (Example 5).

The time unit specifies the unit of measurement for times and delays.

The time precision specifies how delay values should be rounded during the simulation.

The time precision value should be equal or smaller than the time unit value.

Both time precision and time unit should be made up of an integer number and a character string that represent a unit of time. The valid numbers are: 1, 10, and 100. The valid characters are:
s, ms, us, ns, ps, and fs.

Actual time units and time precision values can be displayed by the $printtimescale system task.

`unconnected_drive and `nounconnected_drive

These compiler directives define how unconnected input ports of modules should be treated. They should be enclosed between pair of `unconnected_drive and`nounconnected_drive directives (Example 6).

The `unconnected_drive takes one parameter - pull0 or pull1. If pull0 is used then all unconnected ports will be pulled down. If pull1 is used then all unconnected ports will be pulled up.

These directives should be used outside any module definition.

Examples

Example 1

`celldefine
module my_and(y, a, b);
output y;
input a, b;
  assign y = a & b;
endmodule
`endcelldefine

Module my_and is marked as a cell module.

Example 2

`default_nettype tri

The default net type is set to tri.

Example 3

`define SIZE 8
`define xor_b(x,y) (x & !y)|(!x & y)
//These text macros can be used as follow:
reg [`SIZE - 1 : 0] data_out;
c = `xor_b(a, b);
`undef SIZE

Example 4

`ifdef behavioral
  `include "groupA_beh.v ";
  `include "groupB_beh.v ";
  `include "ctrl_beh.v ";
`else
  `include "groupA_synth.v ";
  `include "groupB_ synth.v ";
  `include "ctrl_ synth.v ";
`endif

If a 'behavioral' text macro is defined in a file then the behavioral models from the files: groupA_beh.v, groupB_beh.v, and ctrl_beh.v, will be included. Otherwise synthesizable models from groupA_synth.v, groupB_synth.v, and ctrl_synth.v, will be included.

Example 5

`timescale 10 ns / 100 ps

The time unit is set to 10 ns. During the simulation all delay values will be multiplied by 10 ns, and all delays will be rounded with 100 ps precision.

Example 6

`unconnected_drive pull1
module my_and(y, a, b);
output y;
input a, b;
  assign y = a & b;
endmodule
module test;
reg b;
wire y;
  my_and u1 (y, ,b);
endmodule
`nounconnected_drive

The a terminal of u1 will be pulled up (set to 1).

Important Notes

• All compiler directives can be set to their default values by `resetall

Comments

Formal Definition

Comments provide a means of describing or documenting a model.

Simplified Syntax

// a single line with comments

/* multiple lines

containing comments */

Description

Comments can be used for describing models. There are two ways of using comments: in a single line or in multiple lines. It is illegal to use '/*' characters without matching '*/' characters. The multiple line comments cannot be nested.

Examples

Example 1

// this is the first line of a single line comment
// this is the second line of a single line comment

Example of a single line comment.

Example 2

/* this is the first line of a multiple line comment
this is the second line of a multiple line comment
*/

Example of a multiple line comment.

Important Notes

• Using the '/*' characters without the matching '*/' characters is not allowed

• The multiple line comments cannot be nested

Conversion Functions

Formal Definition

Conversion functions convert data formats between integer, real and bit representations.

Simplified Syntax

$bitstoreal(bit_number) ;

$itor(integer_number) ;

$realtobits(real_number) ;

$rtoi(real_number) ;

Description

The $bitstoreal function converts a bit pattern to a real number. The $itor function converts an integer to a real number. The $realtobits function converts a real number to its binary a equivalent. The $rtoi function converts a real number to an integer.

Examples

Example 1

reg [31:0] a, result_b ;
integer b, result_I ;
real c, result_r ;
result_r = $bitstoreal(a) ;
result_r = $itor(b) ;
result_b = $realtobits(c) ;
result_I = $rtoi(c) ;

Important Notes

• Conversion functions are not synthesizable.

Continuous Assignments

Formal Definition

Continuous assignments are the most basic assignment in dataflow modeling. Continuous assignments are used to model in combinational logic. It drives values into the nets.

Simplified Syntax

net [strength] [range] [delay] identifier = net or register ;

assign [strength] [delay] net = net or register ;

Description

Continuous assignments provide a way of modeling combinational logic at a higher level of abstraction than Gate-Level logic. It allows the use of Boolean logic rather than gate connections.

The left-hand side of an assignment is a variable to which the right-side value is to be assigned and must be a scalar or vector net or concatenation of both. The right-hand side of an assignment, separated from the left-hand side by the equal (=) character, can be a net, a reg or any expression that evaluates a value including function calls.

Continuous assignments drive values into the nets whenever the right-hand side value changes, this means continuous assignments are always active and assignments occur whenever the right-hand side operands changes. It drives both vector and scalar.

Continuous assignments can be used in two ways: as the net declaration statement and as the continuous assignment statement.

In a continuous assignment statement, after the assign keyword (Example 1) the net is declared as the left-hand side and after the equal (=) character, the right-hand side is declared as an expression. The value of out changes whenever the values of operands In_1 or In_2 change.

Example 2 shows how to use continuous assignments with vectors. The left-hand side of an assignment is a vector net, while the right-hand side operands are vector registers.

The left-hand side of an assignment can also be a concatenation of nets. Example 3 describes this use.

Instead of the continuous assignment statement, the net declaration assignment can be used. This means that in the net declaration statement we can assign expressions that occur whenever right-hand side operands change. In this case, assign keyword is not used. Example 1can be described as shown in Example 4. In this case a net can be declared only once, therefore only one net declaration assignment can be made to a net.

An optional delay given to a continuous assignment specifies the time duration between the right-hand side operand value change and the assignment to the left-hand side. Delay specification can be used both in the continuous assignment statement and the net declaration statement (see Example 5 and Example 6).

Also optional is strength specification. Example 7 shows a way to specify strength in a continuous assignment. For more information about strength see the "Strength" chapter.

Examples

Example 1

wire out;
assign out = In_A & In_B ;

Continuous assignment 'out' is a net. Both In_1 and In_2 are nets.

Example 2

assign address[7:0] = address_1[7:0] ^ address_2[7:0] ;

Continuous assignment with range specification. Address_1 and address_2 are 8-bit vector registers.

Example 3

assign {c_out, sum[7:0]} = Data_A[7:0]+Data_B[7:0]+c_in;

Continuous assignment with concatenation.

Example 4

wire out = In_A & In_B ;

The net declaration assignment. Equivalent to Example 1.

Example 5

assign #25 out = In_A & In_B ;

Delay specification in the continuous assignment statement.

Example 6

wire #25 out = In_A & In_B ;

Delay specification in the net declaration assignment.

Example 7

assign (strong1, pull0) out = Data_A | Data_B ;

Important Notes

· Continuous assignments cannot be used within initial or always blocks.

· Continuous assignment statements can be used on a net that has been previously declared

· Only one net declaration assignment can be used for a net.

· More than one continuous assignment statement can be made to a net.

Case Statement

Formal Definition

The case statement is a decision instruction that chooses one statement for execution. The statement chosen is one with a value that matches that of the case statement.

Simplified Syntax

case (expression)

  expression : statement

  expression {, expression} : statement

default : statement

endcase

casez (expression)

  expression : statement

  expression {, expression} : statement

default : statement

endcase

casex (expression)

  expression : statement

  expression {, expression} : statement

default : statement

endcase

Description

The case statement starts with a case or casex or casez keyword followed by the case expression (in parenthesis) and case items or default statement. It ends with the endcasekeyword. The default statement is optional and should be used only once. A case item contains a list of one or more case item expressions, separated by comma, and the case item statement. The case item expression and the case item statement should be separated by a colon.

During the evaluation of the case statement, all case item expressions are evaluated and compared in the order in which they are given. If the first case item expression matches the case expression, then the statement which is associated with that expression is executed and the execution of the case statement is terminated. If comparison fails, then the next case item expression is evaluated and compared with the case expression. If all comparisons fail and the default section is given, then its statements are executed. Otherwise none of the case items will be executed.

Both case expression and case item expressions should have the same bit length. None of the expressions are required to be a constant expression.

The case expression comparison is effective when all compared bits are identical. Therefore, special types of case statement are provided, which can contain don't-care values in the case expression and in the case item expression. These statements can be used in the same way as the case statement, but they begin with the keywords casex and casez.

The casez statement treats high-impedance (z) values as don't-care values and the casex statement treats high-impedance and unknown (x) values as don't care values. If any of the bits in the case expression or case item expression is a don't-care value then that bit position will be ignored.

The don't-care value can be also specified by the question mark (?), which is equal to z value.

Examples

Example 1

reg [1:0] address;
case (address)
  2'b00 : statement1;
  2'b01, 2'b10 : statement2;
  default : statement3;
endcase

If the address value is 2'b00 then statement1 will be executed. Statement2 is executed when address value equals 2'b01 or 2'b10. Otherwise statement3 is executed.

Example 2

reg a;
case (a)
  1'b0 : statement1;
  1'b1 : statement2;
  1'bx : statement3;
  1'bz : statement4;
endcase

In Example 2, the statements will be executed depending on the value of the 'a' variable (if a = 1'b0 then statement1 will be executed, etc). If we assign a question mark (?) to the 'a' variable, then statement4 will be executed because the syntax concerning numbers defines the question mark as equal to the z value.

Example 3

reg a;
casez (a)
  1'b0 : statement1;
  1'b1 : statement2;
  1'bx : statement3;
  1'bz : statement4;
endcase

If value of variable 'a' is 1'b0 or 1'b1 or 1'bx then statement1, statement2 or statement3 will be executed respectively. If 'a' equals 1'bz or 1'b? then statement1 will be executed because the casez statement treats z and ? as the don't-care values. Statement4 will never be executed because only the first case item, which matches with the case expression, is executed.

Example 4

reg a;
casex (a)
  1'b0 : statement1;
  1'b1 : statement2;
  1'bx : statement3;
  1'bz : statement4;
endcase

If variable 'a' is 1'b0 or 1'b1 then statement1 and statement2 will be executed respectively. If 'a' equals 1'bx or 1'bz or 1'b? then statement1 will be executed (x, z and ? are don't care values for the casex statement). Statement3 and statement4 will never be executed.

Example 5

reg a;
case (1'b1)
  a : statement1;
endcase

The case expression can be a constant expression. In Example 5, statement1 will be executed only if 'a' is equal to 1'b1.

Important Notes

· The default statement is optional and it can appear only once.

· The parenthesis (?) can appear in expressions and it is equal to high-impedance (z) value.

· If don't care values are to be ignored, then the casex or casez statements should be used.

· The case statement can be a group of statements in the begin - end block.

· Both the case expression and case item expressions should have the same length.

· The case statement can appear only within structured procedures.