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Showing posts with label Delays. Show all posts
Showing posts with label Delays. Show all posts

Friday, 5 April 2013

Transition Delay and Propagation Delay

Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum value. This is known as “rise time”.

propagation_delays

Similarly “fall time” can be defined as the time taken by a signal to fall from 90 %( 80%) to the 10 %( 20%) of its maximum value.

Transition is the time it takes for the pin to change state.


Setting Transition Time Constraints

The above theoretical definitions are to be applied on practical designs. Now, the transition time of a net becomes the time required for its driving pin to change logic values (from 10 %( 20%) to the 90 %( 80%) of its maximum value). This transition time used foe delay calculations are based on the timing library (.lib files).

Transition related constraints can be provided in Design Compiler (logic synthesis tool from Synopsys) by using below commands:

1. max_transition : This attribute is applied to each output of a cell. During optimization, Design Compiler tries to make the transition time of each net less than the value of the max_transition attribute.

2. set_max_transition: This command is used to change the maximum transition time restriction specified in a technology library.

“This command sets a maximum transition time for the nets attached to the identified ports or to all the nets in a design by setting themax_transition attribute on the named objects.

For example, to set a maximum transition time of 3.2 on all nets in the design adder, enter the following command:

         set_max_transition 3.2 [get_designs adder]

To undo a set_max_transition command, use the remove_attributecommand. For example, enter the following command:

         remove_attribute [get_designs adder] max_transition”

(Directly quoted from Design Complier user manual)

Setting Capacitance Constraints

The transition time constraints specified above do not provide a direct way to control the actual capacitance of nets. To control capacitance directly, below command has to be used:

set_max_capacitance: This command sets the maximum capacitance constraint on input ports or designs.

In addition to set_max_transition, set_max_capacitance can also be used as this command works independent.

This command applies maximum capacitance limit to output pin or port of the design.

This command can also be used to apply capacitance limit on any net.
Eg:
         set_max_capacitance 4 [get_designs decoder]

To remove the set_max_capacitance command, use theremove_attribute command.

           remove_attribute [get_designs decoder] max_capacitance

 

Propagation Delay

Propagation delay is the time required for a signal to propagate through a gate or net.

Hence if it is cell, you can call it as “Gate or Cell Delay” or if it is net you can call it as “Net Delay”

Propagation delay of a gate or cell is the time it takes for a signal at the input pin to affect the output signal at output pin.

For any gate propagation delay is measured between 50% of input transition to the corresponding 50% of output transition.

There are 4 possibilities:

Propagation delay between 50 % of Input rising to 50 % of output rising.

Propagation delay between 50 % of Input rising to 50 % of output falling.

Propagation delay between 50 % of Input falling to 50 % of output rising.

Propagation delay between 50 % of Input falling to 50 % of output falling.

Each of these delays has different values. Maximum and minimum values of these set are very important. Maximum and minimum propagation delay values are considered for timing analysis.

For net propagation delay is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

Propagation delay is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.

Propagation delay depends on the input transition time (slew rate) and the output load. Hence two dimensional look up tables are used to calculate these delays. How to calculate propagation delay of net and gate? Please refer below articles to find the detailed explanation.

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Sunday, 9 September 2012

Delays

Formal Definition

Delays specify a time in which assigned values propagate through nets or from inputs to outputs of gates.

Simplified Syntax

#value

#(value)

#(value, value)

#(value, value, value)

Description

Delays specify how values propagate through nets or gates.

The net delay declaration specifies a time needed to propagate values from drivers through the net. It can be used in continuous assignments (Example 1) and net declarations (Example 2).

The gate delay declaration specifies a time needed to propagate a signal change from the input of a gate input to its output. The gate delay declaration can be used in gate instantiations (Example 3).

The delays can be also used for delay control in procedural statements (Example 4 - see Procedural timing control for more explanations).

The delays declaration can contain up to three values: rise, fall, and turn-off delays. The default delay is zero. If only one delay value is specified then it is used for all signal changes. If two delays are specified then the first delay specifies the rise delay and the second delay specifies the fall delay. If the signal changes to high-impedance (z) or to unknown (x) then the smaller value will be used. This means that if delays are specified as follows: #(4,3) then the second value (3) will be used for signal changes to z or x value.

If three values are given, then the first value specifies the rise delay, the second specifies the fall delay, and the third specifies turn-off delay. If the signal changes to unknown (x) value, then the smallest of these three values will be used.

Value changes

Delay used for propagation if:

From:

To:

1 delay specified

2 delays specified

3 delays specified

0

1

d1

d1

d1

0

x

d1

min(d1, d2)

min(d1, d2, d3)

0

z

d1

min(d1, d2)

d3

1

0

d1

d2

d2

1

x

d1

min(d1, d2)

min(d1, d2, d3)

1

z

d1

min(d1, d2)

d3

x

0

d1

d2

d2

x

1

d1

d1

d1

x

z

d1

min(d1, d2)

d3

z

0

d1

d2

d2

z

1

d1

d1

d1

z

x

D1

min(d1, d2)

min(d1, d2, d3)

Table 6 Rules for delays depending on number of specified values

Examples

Example 1

assign #5 out = in1 & in2;

All value changes on in1 or in2 signals will propagate to out port in 5 time units.

assign #(1,3) b = ~a;

All value changes on signal 'a' that cause signal 'b' to change its value to '1', will propagate through net 'b' in 1 time unit. If '~a' expression equals 0 then it will take 3 time units to propagate this value through net 'b'. If the result of '~a' expression is unknown (x) or high-impedance (z) value, then it will take 1 time unit (because 1 is less than 3 therefore this value will be used for propagating these value changes).

assign #(5,3,7) w_or = |bus;

If result of right-side expressions is 1 then 5 will be used as the delay.

If result of right-side expressions is 0 then 3 will be used as the delay.

If result of right-side expressions is high-impedance (z) then 7 will be used as the delay.

If result of right-side expressions is unknown (x) then 3 will be used as the delay (because this is the smallest of these three values).

Example 2

wire #(5) ready;
tri #(2,3) a;
wand #(3,2,1) signal_1;

Net ready has only one delay specified.

Net a has two delays specified.

Net signal_1 has three delays specified.

Example 3

and #1 and_gate (o, i1, i2);
or #(5,1) or_gate (o, i1, i2);
bufif1 #(3,4,5) buffer (o, i, c);

The and_gate has one delay specified.

The or_gate has two delays specified.

The buffer has three delays specified.

Example 4

reg r;
initial begin
  #10 r = 1'b1;
  r = #10 1'b0;
end

Important Notes

  • If fewer than 3 delays are specified then the smallest value is used for the missing delay(s).