Formal Definition
The Value change dump (VCD) file contains information about any value changes on the selected variables.
Simplified Syntax
$dumpfile(name)
$dumpvars
$dumpvars(level, list_of_variables_or_modules)
$dumpoff
$dumpon
$dumpall
$dumplimit
$dumpflush
Description
$dumpfile(filename)
This task is used to specify the VCD file name. The filename parameter is optional. If it is not given, then the file will be named "Verilog.dump”.
$dumpvars(level, list_of_variables_or_modules)
This task is used to specify which variables should be dumped. Both parameters are optional and if none are used, then all variables will be dumped.
If level = 0, then all variables within the modules from the list will be dumped. If any module from the list contains module instances, then all variables from these modules will also be dumped.
If level = 1, then only listed variables and variables of listed modules will be dumped.
$dumpoff
This task stops the dumping of variables. All variables are dumped with x value and all next changes of variables will not be dumped.
$dumpon
This task starts previously stopped dumping of variables.
$dumpall
When this task is used, then the current value of all dumped variables will be written to file.
$dumplimit(filesize)
This task can set the maximum size of the VCD file.
$dumpflush
This task can be used to make sure that all changes of dumped variables are written to file.
Examples
module top;
reg a, b;
wire y;
assign y = a & b;
always begin
a = 1'b0;
#10;
a = 1'b1;
#10;
a = 1'bx;
#10;
end
always begin
b = 1'b0;
#30;
b = 1'b1;
#30;
b = 1'bx;
#30;
end
initial begin
$dumpfile("test.txt");
$dumpvars(1,a,y);
#200;
$dumpoff;
#200;
$dumpon;
#20;
$dumpall;
#10;
$dumpflush;
end
endmodule
The dumpfile will contain only changes of 'a' and 'y' variables. After 200 time units, dumping will be suspended for 200 time units. Next, dumping will start again and after 20 time units, all variables will be dumped.
Important Notes
-
Value change dump file can be used for hierarchical monitoring of all signal changes within design modules.
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