Featured post

Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Sunday, 9 September 2012

Simulation Control Tasks

Formal Definition

Simulation control tasks allow you to stop or quit simulation.

Simplified Syntax

$stop [(n)] ;

$finish [(n)] ;

Description

The $stop system task is used to suspend simulation. When invoked it suspends simulation, prints simulation time and prints location. Optional expressions can determine the type of printed message:

Expression (n)

Message

0

No message

1

Simulation time and location

2

Simulation time, location, memory consumption and CPU time used in simulation

By default the value 1 is used.

The $finish system task ends the simulation, exits the simulator and passes control back to the operating system. It can be invoked with the same arguments as the $stop system task and has the same default value.

Examples

Example 1

$stop ;

Suspend simulation and print message (default argument = 1)

Example 2

#150 $finish(2) ;

Exits simulator after 150 time units from the last executed statement and prints message (argument == 2).

Important Notes

  • Remember that $finish control system task makes the simulator exit, however $stop simply suspends simulation.

No comments:

Post a Comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.