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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
integer my_q[$];
integer my_q[$] = {1, 3, 5};
integer my_q[$:127];
int queueA[$:99]; // A queue whose maximum size is 100 integers
// SystemVerilog Queue Operations int q[$] = { 2, 4, 8 }; int p[$]; int e, pos; e = q[0]; // read the first (leftmost) item e = q[$]; // read the last (rightmost) item q[0] = e; // write the first item p = q; // read and write entire queue (copy) q = { q, 6 }; // insert '6' at the end (append 6) q = { e, q }; // insert 'e' at the beginning (prepend e) q = q[1:$]; // delete the first (leftmost) item q = q[0:$-1]; // delete the last (rightmost) item q = q[1:$-1]; // delete the first and last items q = {}; // clear the queue (delete all items) q = { q[0:pos-1], e, q[pos,$] }; // insert 'e' at position pos q = { q[0:pos], e, q[pos+1,$] }; // insert 'e' after position pos
// SystemVerilog Queue Methods module queue_methods(); // Queue is declated with $ in array size integer queue[$] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }; integer i; initial begin $display ("Initial elements in the queue"); print_queue; // Insert new element at begin of queue queue = {11, queue}; $display ("new element added using concatenation"); print_queue; // Insert using method at beginning queue.push_front(12); $display ("new element added using push_front"); print_queue; // Insert using method at end queue.push_back(12); $display ("new element added using push_back"); print_queue; // Using insert to insert, here 6 is index // and 13 is value queue.insert(6,13); $display ("new element added using insert(index,value)"); print_queue; // get first queue element method at begining i = queue.pop_front(); $display ("element poped using pop_front"); print_queue; // get last queue element method at end i = queue.pop_back(); $display ("element poped using pop_end"); print_queue; // Use delete method to delete element at index 4 in queue queue.delete(10); $display ("deleted element at index 10"); print_queue; #1 $finish; end // Method to print queue task print_queue; integer i; $write("Queue contains "); for (i = 0; i < queue.size(); i ++) begin $write (" %g", queue[i]); end $write("\n"); endtask endmodule
1 2 3 | integer dyn_array_1[]; integer dyn_array_1[]; integer multi_dime_dyn_array[][]; |
// SystemVerilog Dynamic arrays module dyn_arr; int dyn[], d2[]; // Empty dynamic arrays initial begin dyn = new[5]; // Allocate 5 elements foreach (dyn[j]) begin dyn[j] = j; // Initialize the elements $display("j = %0d dyn = %0d",j,dyn[j]); end $display("Copy the dynamic array"); // Copy a dynamic array d2 = dyn; $display("dyn[0] = %0d d2[0] = %0d",dyn[0],d2[0]); $display("Modify contents of copy"); // Modify the copy d2[0] = 5; $display("dyn[0] = %0d d2[0] = %0d",dyn[0],d2[0]); $display ("Extend the array length and check previous content"); // Expand and copy dyn = new[20](dyn); $display("dyn[4] = %0d", dyn[4]); $display ("Extend the array length and check previous content"); // Allocate 100 new integers. Old values will lost dyn = new[100]; $display ("dyn[4] = %0d", dyn[4]); // Delete all elements dyn.delete; end endmodule
int data[0:15]; // 16 ints [0]..[15] int address[16]; // 16 ints [0]..[15]
address[15] = 1; // Set last array element
int array2 [0:7][0:3]; // Verbose declaration int array3 [8][4]; // Compact declaration array2[7][3] = 1; // Set last array element
bit [7:0] unpacked_array[3]; // Unpacked array
int ascend[4] = ’{0,1,2,3}; // Initialize 4 elements int decend[5]; int array[2][3] = ’{’{0,1,2}, ’{3,4,5}}; descend = ’{4,3,2,1,0}; // Set 5 elements descend[0:2] = ’{5,6,7}; // Set first 3 elements ascend = ’{4{8}}; // Four values of 8
// SystemVerilog For and Foreach loop to access arrays module array_loops; initial begin bit [31:0] src[5], dst[5]; for (int i=0; i<$size(src); i++) begin src[i] = i; $display("src[%0d] = %0d", i, src[i]); end foreach (dst[j]) begin dst[j] = src[j] * 2; // dst doubles src values $display("dst[%0d] = %0d", j, dst[j]); end end endmodule
// SystemVerilog For and Foreach loop to access arrays module array_loops; int md[2][3]; initial begin $display("Initial value:"); foreach (md[i,j]) // Yes, this is the right syntax $display("md[%0d][%0d] = %0d", i, j, md[i][j]); $display("New value:"); md = '{{9, 8, 7}, {default:5}}; // Replicate last 3 values foreach (md[i,j]) // Yes, this is the right syntax $display("md[%0d][%0d] = %0d", i, j, md[i][j]); end endmodule
1 | bit [3:0] [7:0] bytes; // 4 bytes packed into 32-bits |
1 | bit [3:0] [7:0] barray [3]; // Packed: 3x32-bit |
string StringName = "VLSI Encyclopedia";
// SystemVerilog Strings module str; string S1; string S2; initial begin S1 = "VLSI "; S2 = "Encyclopedia"; $display(" %d ",S1.len() ); $display(" %s ",S2.getc(5) ); $display(" %s ",S1.tolower); $display(" %s ",S2.toupper); $display(" %d ",S2.compare(S1) ); $display(" %d ",S1.compare("VLSI") ); $display(" %s ",S1.substr(2,3) ); S1 = "111"; $display(" %d ",S1.atoi() ); end endmodule
// SystemVerilog String Pattern Matching program main; string S1,S2; initial begin S1 = "String matching in SystemVerilog"; S2 = "String"; if(match(S1,S2)) $display(" S2 : %s : found in :%s:",S2,S1); S2 = "SystemVerilog"; if(match(S1,S2)) $display(" S2 : %s : found in :%s:",S2,S1); S2 = "String matching"; if(match(S1,S2)) $display(" S2 : %s : found in :%s:",S2,S1); S2 = "matching in "; if(match(S1,S2)) $display(" S2 : %s : found in :%s:",S2,S1); S2 = "String matching in SystemVerilog"; if(match(S1,S2)) $display(" S2 : %s : found in :%s:",S2,S1); end endprogram function match(string s1,s2); int len1,len2; len1 = s1.len(); len2 = s2.len(); match = 0 ; if( len2 > len1 ) return 0; for(int i = 0;i < len1 - len2 + 1; i ++) if( s1.substr(i,i+len2 -1) == s2) return 1; endfunction
// SystemVerilog Strings Equality module str; string S1 = "VLSI Encyclopedia"; string S2 = "VLSI Encyclopedia"; string S3 = "vlsi encyclopedia"; initial begin if(S1 == S2) $display(" S1 and S2 are equal"); else $display(" S1 and S2 are not equal"); if(S1 == S3) $display(" S1 and S3 are equal"); else $display(" S1 and S3 are not equal"); end endmodule
// SystemVerilog Strings Equality module str; string S1 = "VLSI Encyclopedia"; string S2 = "VLSI Encyclopedia"; string S3 = "vlsi encyclopedia"; initial begin if(S1 != S2) $display(" S1 and S2 are not equal"); else $display(" S1 and S2 are equal"); if(S1 != S3) $display(" S1 and S3 are not equal"); else $display(" S1 and S3 are equal"); end endmodule
// SystemVerilog Strings Concatenation module str; string S1, S2, S3, S4, S5; initial begin S1 = "Con"; S2 = "cate"; S3 = ""; S4 = "na"; S5 = "tion"; $display(" %s ",{S1,S2,S3,S4,S5}); end endmodule
// SystemVerilog Strings Replication module str; string S1, S2; initial begin S1 = "w"; S2 = ".vlsiencyclopedia.com"; $display(" %s ",{{3{S1}},S2}); end endmodule
// SystemVerilog Strings Indexing module str; initial begin string S1; S1 = "Indexing"; for(int i =0 ;i < 8 ; i++) $display("%s ",S1[i]); end endmodule
// Constant bit const bit [63:0] data_bus='hB6AB31E0; // Constant int bus width const int bus_width = 8; // Constant String VLSI Encyclopedia const string name = "VLSI Encyclopedia"; // Constant method function int count (const ref bytes[]);
module enum_method; typedef enum {RED,BLUE,GREEN} colour; colour c; initial begin c = c.first(); $display(" %s ",c.name); c = c.next(); $display(" %s ",c.name); c = c.last(); $display(" %s ",c.name); c = c.prev(); $display(" %s ",c.name); end endmodule
typedef enum {FIRST=1, SECOND, THIRD} ordinal_e; ordinal_e position;
typedef enum {ERR_O=0, FIRST=1, SECOND, THIRD} ordinal_e; ordinal_e position;
module enum_method; typedef enum {RED, BLUE, GREEN} COLOR_E; COLOR_E color, c2; integer c; initial begin c = color; // Convert from enum to integer c++; // Increment integer if (!$cast(color, c)) begin // Cast integer back to enum $display("Cast failed for c=%0d", c); end $display("Color is %0d & %0s", color, color.name); c2 = COLOR_E'(c); // No type checking done end endmodule
It just got a lot easier to build wearable gadgets that aren’t so bulky or awkward.
Intel CEO Brian Krzanich showed off a minuscule computer, dubbed Curie, during a keynote speech at the International Consumer Electronics Show in Las Vegas on Tuesday. Krzanich plucked a button off his blazer before explaining that it contained a Curie demo module.
Curie is a sure sign that hardware makers are eager to build wearable devices of all kinds. It also points to the unwelcome size of many existing smart watches and smart glasses.
Intel’s new device will include a Bluetooth low-energy radio, motion sensors, and components designed to rapidly and precisely differentiate between different types of physical activity. Krzanich said Curie will run “for extended periods of time” on a coin-size battery and would be available in the second half of the year.
Curie appeared much smaller than a postage-stamp-size computer, called Edison, that Krzanich showed off at last year’s CES.
The world’s largest chip maker evidently sees wearables as one of the most important categories in consumer electronics. It’s a belief held by a lot of other companies at CES, where gadgets meant to be worn on the body or clipped to clothing were all over the show floor this year (see “CES 2015: Wearables Everywhere”).
To make it clear that Curie is already functional, the company built a simple step-tracking smartphone app to go with the module Krzanich had on him; at one point he pulled the phone out of his pocket, and its display indicated he’d taken 1,788 steps during the keynote.
As part of its wearables push, Intel has partnered with a number of companies in the fashion and accessories businesses, including Luxottica Group, which is the world’s largest eyeglass maker with brands such as Ray-Ban and Oakley. Krzanich said Luxottica will use Curie to make “truly consumer-friendly” smart glasses—a notoriously tricky thing to do, in part because of the size of components needed to make them work.
Oakley CEO Colin Baden joined Krzanich on stage to talk about wearables, which Oakley has built in the form of devices like ski goggles that include a head-up display. When you put a wearable device on your face, Baden said, it becomes part of your personality. “It’s important the form factor compress so the electronic component of it doesn’t become burdensome,” he said.