Transition Delay and Propagation Delay

Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum value. This is known as “rise time”.

Similarly “fall time” can be defined as the time taken by a signal to fall from 90 %( 80%) to the 10 %( 20%) of its maximum value.

Transition is the time it takes for the pin to change state.

Setting Transition Time Constraints

The above theoretical definitions are to be applied on practical designs. Now, the transition time of a net becomes the time required for its driving pin to change logic values (from 10 %( 20%) to the 90 %( 80%) of its maximum value). This transition time used foe delay calculations are based on the timing library (.lib files).

Transition related constraints can be provided in Design Compiler (logic synthesis tool from Synopsys) by using below commands:

1. max_transition : This attribute is applied to each output of a cell. During optimization, Design Compiler tries to make the transition time of each net less than the value of the max_transition attribute.

2. set_max_transition: This command is used to change the maximum transition time restriction specified in a technology library.

“This command sets a maximum transition time for the nets attached to the identified ports or to all the nets in a design by setting themax_transition attribute on the named objects.

For example, to set a maximum transition time of 3.2 on all nets in the design adder, enter the following command:

         set_max_transition 3.2 [get_designs adder]

To undo a set_max_transition command, use the remove_attributecommand. For example, enter the following command:

         remove_attribute [get_designs adder] max_transition”

(Directly quoted from Design Complier user manual)

Setting Capacitance Constraints

The transition time constraints specified above do not provide a direct way to control the actual capacitance of nets. To control capacitance directly, below command has to be used:

set_max_capacitance: This command sets the maximum capacitance constraint on input ports or designs.

In addition to set_max_transition, set_max_capacitance can also be used as this command works independent.

This command applies maximum capacitance limit to output pin or port of the design.

This command can also be used to apply capacitance limit on any net.
Eg:
         set_max_capacitance 4 [get_designs decoder]

To remove the set_max_capacitance command, use theremove_attribute command.

           remove_attribute [get_designs decoder] max_capacitance

 

Propagation Delay

Propagation delay is the time required for a signal to propagate through a gate or net.

Hence if it is cell, you can call it as “Gate or Cell Delay” or if it is net you can call it as “Net Delay”

Propagation delay of a gate or cell is the time it takes for a signal at the input pin to affect the output signal at output pin.

For any gate propagation delay is measured between 50% of input transition to the corresponding 50% of output transition.

There are 4 possibilities:

Propagation delay between 50 % of Input rising to 50 % of output rising.

Propagation delay between 50 % of Input rising to 50 % of output falling.

Propagation delay between 50 % of Input falling to 50 % of output rising.

Propagation delay between 50 % of Input falling to 50 % of output falling.

Each of these delays has different values. Maximum and minimum values of these set are very important. Maximum and minimum propagation delay values are considered for timing analysis.

For net propagation delay is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

Propagation delay is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.

Propagation delay depends on the input transition time (slew rate) and the output load. Hence two dimensional look up tables are used to calculate these delays. How to calculate propagation delay of net and gate? Please refer below articles to find the detailed explanation.

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Tips for an Error-free Functional Simulation

Getting a VHDL code to work in the functional simulation is not always an easy task.This article will cover some tips to quickly point out the errors in the code and make your life easier.

1. Create a proper sensitivity list. Some times you may have to add other control signals too(other than clock) into you sensitivity list to get is working.
2. Initialize the signals and variables correctly. If they are not initialized(normally they are set to '0'), then these signals will appear as "U"in the simulation waveform.
3. If you see "X" in the waveform then that indicates concurrent writing to the same signal. A simple re-arrangement of the signal inside the process will normally take out this bug.
4. In case you have arrays in the design make sure to check for out of bound error. This happens when you read or write a different index than the one available within the range of array.
5. If elsif's are error prone. Always try to consider all the conditions of If elsif. If a particular condition is not considered then the value will remain unchanged. If you don’t want this to happen then make sure you reset the signal, using an else condition.
6. Within a process, signal assignments can be written in any order. They will get executed concurrently. But for variables, the order matters. line 1 is executed first, line 2 second and so on...
7. One way to debug the code is to force one or more signals as constants and test the design. This will help you in localizing the error.
8. Writing a location in RAM requires a small time delay. Account for this, while reading and writing from the same location in the same clock cycle. The read data will be the one written in the last clock cycle.
9. Try synthesizing the design. The synthesizer tool may give out some warnings or errors which will point you in the correct direction to solve the error in the functional simulation.
10. When using components in the design, use name instantiation, so that you don't accidentally assign wrong signals to the component ports.

VLSI Interview Questions-1

1.What is the difference between mealy and moore state-machines.
2.How to solve setup and hold violations in the design.
3.What is antenna violation & ways to prevent it.
4.We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage.
5.What is tie-high and tie-low cells and where it is used.
6.What is the difference between latches and flip-flops based designs.
7.What is High-Vt and Low Vt cells.
8.What is LEF mean?
9.What is DEF mean?
10.Steps involved in designing an optimal padring.
11.What is metastability and steps to prevent it.
12.What is local-skew, global skew and useful skew.
13.What are the various timing-paths which i should take care in my STA runs?
14.What are the various components of leakage-power.
15.What are the various yield losses in the design.
16.What is meant by virtual clock definition and why do i need it.
17.What are the various variations which impacts timing of the design.
18.What are the various Design constraints used, while performing synthesis for a design.
19.Specify few verilog constructs which are not supported by the synthesis tool.
20.What are the various capacitances with an MOSFET?
21.Vds-Ids curve for an MOSFET, with increasing Vgs.
22.Explain basic operation of an MOSFET.
23.what is channel length modulation.
24.what is body effect.
25.what is latchup in CMOS design and ways to prevent it?
26.what are the various design changes you do to meet design power targets.
27.what is meant by library characterization.
28.what is meant by wireload model.
29.what are the measures to be taken to design for optimized area.
30.what all will you be thinking while performing floorplan.
31.what are the measures in the design taken for meeting signal integrity targets.
32.what are the measures taken in the Design achieving better yield.
33.what are the measures or precautions to be taken in the design when the chip has both analog and digital portions..
34.what are the steps incorporated for Engineering Change order[ECO].
35.what are the steps performed to achieve Lithography friendly Design.
36.what does synthesis mean?
37.what are the pre-requistes to perform synthesis.
38.Can you explain the synthesis flow.
39.what are the various ways to reduce clock insertion delay in the design.
40.what are the various functional verification methodologies.
41.what does formal verification mean.
42.How will you time the output path in STA.
43.How will you time the input path in STA.
44.What is false path mean in STA and in what scenarios falsepath can come.
45.What does multicycle path mean in STA and in what scenarios MCP can come.
46.What are source synchronous paths in STA.
47.Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it..
48.we have multiple instances in RTL, do you do anything special during synthesis stage.
49.What do you call an event and when do you call an assertion.

Dynamic Timing Analysis

Dynamic timing analysis verifies circuit timing by applying test vectors to the circuit. This approach is an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths.

The most common dynamic timing analysis is the so-called min-max analysis method. Under min-max timing analysis, both minimum and maximum delays of circuit components are used to generate outputs, which are ranges (the spread of earliest data and latest arrival data) instead of edges. Since outputs are in turn fed into inputs, managing the ranges (merging them) can become very complex. As can be seen, if both min version & max version of the delays must be used, the simulation speed will be extremely slow.

Another major issue with dynamic timing analysis is the incomplete coverage. It may only check circuitry that is exercised by test stimulus, which may leave critical paths untested, and timing problems undiscovered. It is also not path oriented. Since dynamic timing analysis reports errors on a certain pin at a certain time, the user must trace through the schematic to locate the path that caused the problem (difficult for large designs).

Finally this method requires development time for test vectors. Dynamic timing analysis tools often track more information than logic simulators, making their performance slower. Also each component must contain both timing information and a functional model before timing verification can proceed. This could prevent the use of new parts that do not have functional models.

It should be noted that min-max simulation is not currently used in the industry. Instead, either functional simulation with timing (timing simulation) or formal verification method is typically used to verify complex IC designs. Typically people use the max version of delays to verify the circuit works under worst-case timing (no setup issues) and min version of the delays to verify best-case timing (no hold issues).

Advantages:
1. Extends coverage of circuit simulation (edges to region).
2. Evaluates worst-case timing using both min. and max. delay values for components.
3. Uses the same test stimulus as logic simulation.
4. Does not report false errors.

Disadvantages:
1. It is not complete.
2. It is not path oriented.
3. It is slower than logic simulation and may require additional test stimulus.
4. It requires functional behavioral models.

Dynamic timing analysis extends logic simulation by reporting violations in terms of simulation times and states. To test circuit timing using worst-case conditions, dynamic timing analysis evaluates the circuit using minimum and maximum propagation delays for each component for each component in the design.

Since dynamic timing analysis performs a simulation, it can use the same stimulus as a logic simulation. Because the stimulus functionally exercises the design, false errors of unused or uninteresting paths are not tested. Note a timing simulation reports results differently than a logic simulation. A logic simulation reports results as edge times and a timing simulation reports results as regions of ambiguity. The results of a timing simulation do not specify exactly when an event occurs, they specify a range of time in which an event can occur.

Static Timing Analysis

Static timing analysis verifies circuit timing by “adding up propagation delays along paths between clocked elements” in a circuit. It checks the delays along each path against the specified timing constraints for each circuit path and reports any existing timing violations. Static timing analysis tools can determine and report timing statistics such as the total number of paths, delays for each path and the circuit’s most critical paths. As design complexity increases, performing timing analysis manually becomes extremely difficult and sometimes even impossible. With increasing popularity of HDL based design methodologies, static timing analysis becomes increasingly popular among digital logic designers. To summarize, both static and dynamic timing analysis methods offer tradeoffs. One is not a replacement for the other. However, the static timing analysis method offers more complete coverage, little overhead, and the ability to report errors in terms of the design schematic.

Advantages:
1.It resembles manual analysis methods.
2. It is path oriented and finds all setup and hold violations.
3. It does not require stimulus or functional models.
4. It is faster than simulation. (for the same amount of coverage).

Disadvantages:
1. It can report false errors.
2. It cannot detect timing errors related to logical operation.

Static timing analysis is similar to manual analysis process, except that it is automated. This allows the design to be analyzed much faster. This makes it possible for a designer to experiment with different synthesis options and constraints in a short time. This method is also complete because it traces and evaluates all paths in a design, not just those exercised by test stimulus.

Because static timing analysis does not perform logic simulation, test stimulus and functional models are not required. This makes static analysis available earlier since development time for stimulus and models are not required.

The modeling requirements for a static analysis tool are relatively simple. However, timing information for each component in the design is required and the designer must specify waveform information about the input data and clock signals the design uses. The component timing information can be found in parts libraries or data books. Such timing information typically include: pin-to-pin delays, setup, hold time specifications and signal inversion information, and clock frequency constraints. Clock and data waveforms are a normal requirement of the design process, and do not require additional development time.

The major drawback of a static timing analysis tool is that it reports false errors. By checking all possible paths in a design, static timing analysis ensures that all possible setup and hold violations in the circuit have been found. However, the potential to detect some false errors exists since circuit behavior is not considered during the analysis. Static analysis tools cannot detect timing errors related to logical operation. Because static timing analysis does not perform functional testing, it cannot detect timing errors, such as race conditions, that are based on the logical operation of the circuit.

Difference between Static and Dynamic timing analysis

Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. The problem is that the simulations vector not can guarantee 100% coverage. The goal for the dynamic analysis is to get a 100% coverage. Dynamic timing simulation is still preferred for non-synchronous logic style. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.

Static timing analysis on the other hand check all path in the circuit even the false paths. False paths are paths that are not possible or interesting in actual operation of the circuit. Therefore you can say that static analysis starts above 100% and works towards 100% by detecting and excluding the false paths. Static tools have made major advancements in recent years, in fact all synthesis tools use static timing analysis internally. Something good about this approach is that almost all tools using it supports multi-cycle paths, in which a path delay constraint exceeds a single clock period. Everything isn't just good, many static timing tools have problems with feedback loops.

Read more ....

Timing Analysis

Depending on the design methodologies used, three types of timing analysis methods are commonly used:

1. Manual analysis
2. Static timing analysis
3. Dynamic timing analysis

Latch based designs are not common in large-scale integration; a separate section latch based static timing analysis which will be covered in later posts.

Manual Analysis: Manual analysis consists of taking a schematic or a netlist to determine the times signals arrive or leave at the input and output ports of the design, and calculating the delay time for the path by adding up the delay times for each component in the path. The objective of the process is to ensure that all signals meet the circuit constraints. This method works well for simple circuits and it is undesirable for large or iterative design process.

Static Timing Analysis: Static timing analysis verifies circuit timing by adding up propagation delays along paths between clocked elements in a circuit. It checks the delays along each path against the specified timing constraints for each circuit path and reports any existing timing violations. Static timing analysis tools can determine and report timing statistics such as the total number of paths, delays for each path and the circuit’s most critical paths...... Read more

Dynamic Timing Analysis: Dynamic timing analysis verifies circuit timing by applying test vectors to the circuit. This approach is an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths...... Read more