2017 VLSI Symposia on VLSI Techology and Circuits

For the past 30 years, the combined annual Symposia on VLSI Technology and Circuits have provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees. A single registration enables participants to attend both Symposia.

Online paper submission:

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits, to be held at the Rihga Royal Hotel in Kyoto, Japan from June 5 – 8, 2017. In a departure from previous years, both Symposia (VLSI Technology and VLSI Circuits) will be held on a fully overlapping schedule from June 6 – 8, preceded by Short Courses on June 5.

The deadline for paper submissions to both Symposia is January 23, 2017. Complete details for paper submission can be found online at: http://vlsisymposium.org/authors.html

This year’s Symposia theme is “Harmonious Integration Toward Next Dimensions.” Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module level, with co-optimization of device technology and circuit/system design, including focus areas in the Internet of Things (IoT), industrial electronics, ‘big data’ management, artificial intelligence (AI), biomedical applications, virtual reality (VR) / augmented reality (AR), robotics and smart cars. These topics will be featured in focus sessions as part of the program.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

• IoT systems & technologies, including ultra-low power, heterogeneous integration, wearable devices, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
• Stand-alone & embedded memories, including technology & reliability for DRAM, SRAM, (3D-)NAND, MRAM, PCRAM, ReRAM and emerging memory technologies
• CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
• RF / analog / digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
• Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
• Packaging technologies & System-in-Package (SiP), including through-silicon vias (TSVs), power & thermal management, inter-chip communication, 3D-system integration, as well as yield & test issues
• Photonics Technology & ‘Beyond CMOS’ devices

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

• Digital circuits, processors and architectures, including circuits and techniques for standalone and embedded processors
• Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
• Frequency generation and clock circuits for high-speed digital and mixed-signal applications
• Analog and mixed-signal circuits, including amplifiers, filters and data converters
• Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
• Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
• Power conversion circuits, including battery management, voltage regulation, and energy harvesting
• Imagers, displays, sensors, VLSI circuits & systems for biomedical, healthcare and wearable applications

Joint Technology & Circuits focus sessions feature invited and contributed papers highlighting innovations and advances in the following areas of joint interest:

• IoT /ULP (Internet of Things / Ultra Low Power) devices: Advanced CMOS processes for ULP, design enablement, design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
• New Computing: Artificial intelligence, ‘beyond von Neumann’ computing, machine learning, neuromorphic & in-memory / in-sensor computing
• 2D MOSFETs / New concepts for channel & gate materials: Graphene, MoS2, α-Si / poly-Si or flexible organic materials for ‘More than Moore’ devices
• Emerging memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, and MRAM, Memristor, 3D Xpoint memory technologies
• Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
• 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and applications

Best Student Paper Award

Awards for best student paper at each Symposia are chosen based on the quality of the papers and presentations. The recipients will receive a monetary award, travel cost support and a certificate at the opening session of the 2018 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

Sponsoring Organizations

The Symposium on VLSI Technology is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society.

The Symposium on VLSI Circuits is sponsored by the IEEE Solid State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society.

Further Information, Registration and Official Call for Papers

Visit: http://www.vlsisymposium.org.

International Conference on VLSI Design and Embeded Systems - Jan 2016

Friends, get yourself ready for the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems which will be held during January 4-8, 2016 at Kolkata, West Bengal, India.

The theme for the conference this year is "Technologies for a Safe and Inclusive World". This 5 day conference comprises: first three days (January 4 to 6, 2016) of main conference followed by Tutorials during the last two days (January 7-8, 2016).

The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on healthcare, environment, energy, transportation, and disaster management. The 29th International Conference on VLSI Design and the 15th International Conference on Embedded Systems will bring together industry and academia to present front-end technology under the theme of Technologies for a Safe and Inclusive World.

The Technical tracks will be grouped under the theme track and the three broad categories namely, Design Methodologies and Technology, Design Tools and EDA and Embedded System Design and Tools. The conference proceedings will be published by the IEEE Computer Society Press. Selected papers from this conference will also be published as special issues of top archival journals. 

Authors are invited to submit full-length (6 pages maximum) in IEEE CS proceedings format, original, unpublished papers with an abstract (200 words maximum) under the tracks listed below. To enable double blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be excluded from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication. 

Track: Design Methodology and Technology 

D1: System-level Design 

ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures 

D2: Advances in Digital Design 

Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes 

D3: Analog / RF Design 

Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design 

D4: Power Aware Design 

Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools 

D5: Devices / Circuits 

New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation 

D6: Emerging Technologies 

Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing 

Track : Design Tools and EDA 

T1: Design Verification 

Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies 

T2: Test Reliability and Fault-Tolerance 

DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design 

T3: Computer-Aided Design (CAD) 

Hardware/software co-design, logic and behavioural synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction) 

Track : Embedded System Design and Tools 

E1: Embedded Systems 

Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies 

E2: FPGA Design and Reconfigurable Systems 

FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping 

E3: Wireless Systems 

Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging 

Theme Track : Technologies for a Safe and Inclusive World 

H1: Technologies for Healthcare Applications 

H2: Technologies for Smart Management of Energy Systems 

H3: Technologies for Intelligent and Secure Transportation Systems 

H4: Technologies for Safety Assurance of Embedded Circuits and Systems 

H5: Technologies for Secure Embedded Circuits and Systems 

Proposals for Tutorials and Special Sessions/Panel Discussion on the above-listed topics (but not limited to) are invited. Please check conference website for details. 

Important dates are the following: 

REGULAR PAPERS 

Abstract submission : July 19, 2015 (Sunday) 

Full Paper submission : July 26, 2015 (Sunday) 

Acceptance Notification : Sep 26, 2015 (Saturday) 

Camera-ready version : Oct 11, 2015 (Sunday) 

TUTORIALS 

Tutorial Proposals : July 19, 2015 (Sunday) 

Acceptance Notification : Sep 26, 2015 (Saturday) 

Presentation Slides : Nov 15, 2015 (Sunday) 

SPECIAL SESSIONS 

Proposal submission : July 19, 2015 (Sunday) 

General Chairs 

Pradip Bose, IBM 

Susmita Sur-Kolay, ISI 

Vice-General Chairs 

Indranil Sengupta, IITKGP 

Parthasarathi Dasgupta, IIMC 

Program Chairs 

Krishnendu Chakrabarty, Duke 

Pallab Dasgupta, IITKGP 

Partha P. Das, IITKGP 

Tutorial Chairs 

Hafizur Rahaman, IIEST 

Prabhat Mishra, UF 

Annajirao Garimella, Intel 

Publiciy chairs 

Chandan Giri, IIESTS 

Ken Stevens, U. Utah 

Monica Pereira, UFRN 

Robert Wille, U. Bremen 

Swarup Bhunia, CWRU 

T. -Y. Ho, NCKU

VLSID 2013 - 26th International Conference on VLSI Design 2013

Venue: Hyatt Regency, Pune, India

This joint conference is a forum for researchers and designers to present and discuss current topics in VLSI design, electronic design automation, embedded systems, and enabling technologies. Two days of tutorials will be followed by three days of regular paper sessions, special sessions, and embedded tutorials. Industry presentation sessions along with exhibits, panel discussions, Design Contest, and Education Forum round off the program.

The theme for the conference is Green Technology - A New Era for Electronics, which explores the ability of VLSI and embedded circuits and systems to positively impact the environment. Example areas under the theme include (but are not restricted to) designing energy-efficient VLSI circuits, improving the efficiency of energy-hungry applications such as data centers, developing intelligent monitoring and control systems such as smart grids, and using integrated circuits or embedded systems to leverage novel green technologies.

Pune city, also known as the Oxford of the East, has witnessed huge growth in its VLSI and embedded community over the past few years and is proud to host its very first VLSI Design Conference. The conference organizing committee is looking forward to making this an unforgettable experience for all attendees.

Conference Program:

Day 1	:	5th January 2013	:	Tutorial
Day 2	:	6th January 2013	:	Tutorial
Day 3	:	7th January 2013	:	Inaugural, Technical Sessions, Student
Day 4	:	8th January 2013	:	Valedictory/Award, Technical Sessions, Student Conference
Day 5	:	9th January 2013	:	Technical Sessions, RASDAT 2013 workshop
Day 6	:	10th January 2013	:	RASDAT 2013 workshop

Proposal submission links now available!
Papers, Tutorials, User/designer track submissions, Design contest and Embedded Tutorials, Special Sessions, Panels.
Deadline for Regular Paper submission has been extended to 24th July, 2012. Please submit Tutorial, User/designer track submissions, Design contest and Embedded Tutorials, Special sessions, Panels proposals by 2nd August, 2012.

Important Dates:

Paper Submissions	:	24th July, 2012
Tutorial Submissions	:	2nd August, 2012
User/Designer Submissions	:	2nd August, 2012
Call for embedded tutorials, special sessions, and panels	:	2nd August, 2012
Design Contest Submission	:	15th September, 2012
Acceptance of notification	:	7th September, 2012
Camera ready paper due	:	1st October, 2012

URL: http://www.vlsidesignconference.org/

Silver jubilee of annual VLSI Design Conference in Hyderabad

The 25th International Conference on VLSI Design and the 11th International Conference on Embedded Systems is being held during January 7 – 11, 2012 at Hyderabad.

This year marks the silver jubilee of the VLSI Design Conference and therefore features an overview of the history of the conference by Vishwani D. Agarwal from Auburn University. The theme this year is Embedded solutions for emerging markets – consumer, energy and automotive.

Jaswinder Ahuja, of Cadence India, and President, VLSI Society of India, delivers the opening keynote on 'Semiconductor industry: Best of times, worst of times, and nowhere else would I rather be!'

Emerging Trends in Process Technologies by Jean Boufarhat of AMD and Samarjit Chakraborty of the Technical University of Munich, Germany, on Challenges in Automotive Cyber-physical Systems Design are two other lectures.

The conference, which features tutorials on 7-8, 2012, really gets going during January 9-11, 2012 and will also see a panel discussion on SoC Realization – A Bridge to New Horizons or a Bridge to Nowhere?

Among other attractions are Intel's Ravi Kuppuswamy on 15 billion by 2015 - Transformation of Embedded Devices to Intelligent Systems; Rajesh Gupta from the University of California San Diego on The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines; Berty Gyselinckx from IMEC, Belgium on A wireless sensor a day keeps the doctor away; Sri Parameswaran from the University of New South Wales on Security and Reliability in Embedded Systems and, Suresh Menon of Xilinx on the FPGA Roadmap: Technology Chalenges and Transitioning to Stacked Silicon Interconnect.

The guest lecture is to be delivered by Rajeev Madhavan, chairman and CEO, Magma Design Automation on The future of Semiconductor Design; What the Indian Electronics Industry can learn from Apple.

Meanwhile, The 3rd IEEE International Workshop on Realiability Aware System Design and Test is also being held at Hyderabad during 7-8, 2012 at Hyderabad, in conjunction with the VLSI Design Conference.