4μm thick fabric like flexible circuit

According to the Korea Advanced Institute of Science and Technology (KAIST), complete with substrate, an active matrix for a flexible display need only be 4μm thick. 

Initially on a sacrificial laser-reactive substrate the matrix of ultra-thin n-type transparent oxide thin-film transistors (TFTs) were fabricated for the back plane.

Laser irradiation from the backside of the substrate split off only the oxide TFT array as a result of reaction with the laser-reactive layer.

The free transistors were transferred to a 4μm  polyethylene terephthalate (PET) substrate, and then the combination was further transferred con-formally to the surface of human skin and artificial leather to demonstrate the possibility of the wearable application.

“The attached oxide TFTs showed high optical transparency of 83% and 40cm2/Vs even under several cycles of severe bending tests,” said KAIST.

The method is called inorganic-based laser lift-off (ILLO).

“By using our ILLO process, the technological barriers for high performance transparent flexible displays have been overcome at a relatively low cost by removing expensive polyimide substrates. Moreover, the high-quality oxide semiconductor can be easily transferred onto skin-like, or any flexible, substrate for wearable application,” said Professor Keon Jae Lee.

Con-formal displays are a potential application.

“With the advent of the Internet of Things era, demand has grown for wearable and transparent displays that can be applied to fields such as augmented reality and skin-like thin flexible devices,” said KAIST. “However, previous flexible transparent displays have poor transparency and low electrical performance. To improve the transparency and performance, past research efforts have tried to use inorganic-based electronics, but the fundamental thermal instabilities of plastic substrates have hampered the high temperature process, an essential step necessary for the fabrication of high performance electronic devices.”

IBM steps forward to replace Silicon Transistors with Carbon Nanotubes

Carbon Nanotube

The breakthrough is that - IBM improves carbon nanotube scaling below 10nm. How ever before calling it as breakthrough we should also check out what other giants like Intel, AMD, TSMC or Samsung is working on. This breakthrough has relation with the Moore's Law. Yes you got right..!!It says that the transistor counts double only every 18 month or so. It’s the time that Intel marks 40 years of the 4004 microprocessor and here now lying some fear that progress will soon hit a wall.

You can refer to my post History and Evolution of Integrated Circuits where it shows clear progress of semiconductor industry.

But not to worry, IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips to support Moore's law. These chips will be both faster and more power efficient.

Few glimpse of carbon nanotube transistors

• Carbon nanotube transistors can operate at ten nanometers
• Equivalent to 10,000 times thinner than a strand of human hair
• Less than half the size of today’s leading silicon technology
• Could also mean wearables that attach directly to skin and internal organs

Here I have an animation for Animated Nanofactory in Action.

As a result of this the devices will become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now.

These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away.

A project at IBM is now aiming to have transistors built using carbon nanotubes ready to take over from silicon transistors soon after 2020. According to the semiconductor industry’s roadmap, transistors at that point must have features as small as five nanometers to keep up with the continuous miniaturization of computer chips.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology.

IBM's new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry.

By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

IBM’s chosen design uses six nanotubes lined up in parallel to make a single transistor. Each nanotube is 1.4 nanometers wide, about 30 nanometers long, and spaced roughly eight nanometers apart from its neighbors. Both ends of the six tubes are embedded into electrodes that supply current, leaving around 10 nanometers of their lengths exposed in the middle. A third electrode runs perpendicularly underneath this portion of the tubes and switches the transistor on and off to represent digital 1s and 0s.

The IBM team has tested nanotube transistors with that design, but so far it hasn't found a way to position the nanotubes closely enough together, because existing chip technology can’t work at that scale. The favored solution is to chemically label the substrate and nanotubes with compounds that would cause them to self-assemble into position. Those compounds could then be stripped away, leaving the nanotubes arranged correctly and ready to have electrodes and other circuitry added to finish a chip.

International Conference on VLSI Design and Embeded Systems - Jan 2016

Friends, get yourself ready for the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems which will be held during January 4-8, 2016 at Kolkata, West Bengal, India.

The theme for the conference this year is "Technologies for a Safe and Inclusive World". This 5 day conference comprises: first three days (January 4 to 6, 2016) of main conference followed by Tutorials during the last two days (January 7-8, 2016).

The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on healthcare, environment, energy, transportation, and disaster management. The 29th International Conference on VLSI Design and the 15th International Conference on Embedded Systems will bring together industry and academia to present front-end technology under the theme of Technologies for a Safe and Inclusive World.

The Technical tracks will be grouped under the theme track and the three broad categories namely, Design Methodologies and Technology, Design Tools and EDA and Embedded System Design and Tools. The conference proceedings will be published by the IEEE Computer Society Press. Selected papers from this conference will also be published as special issues of top archival journals. 

Authors are invited to submit full-length (6 pages maximum) in IEEE CS proceedings format, original, unpublished papers with an abstract (200 words maximum) under the tracks listed below. To enable double blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be excluded from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication. 

Track: Design Methodology and Technology 

D1: System-level Design 

ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures 

D2: Advances in Digital Design 

Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes 

D3: Analog / RF Design 

Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design 

D4: Power Aware Design 

Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools 

D5: Devices / Circuits 

New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation 

D6: Emerging Technologies 

Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing 

Track : Design Tools and EDA 

T1: Design Verification 

Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies 

T2: Test Reliability and Fault-Tolerance 

DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design 

T3: Computer-Aided Design (CAD) 

Hardware/software co-design, logic and behavioural synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction) 

Track : Embedded System Design and Tools 

E1: Embedded Systems 

Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies 

E2: FPGA Design and Reconfigurable Systems 

FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping 

E3: Wireless Systems 

Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging 

Theme Track : Technologies for a Safe and Inclusive World 

H1: Technologies for Healthcare Applications 

H2: Technologies for Smart Management of Energy Systems 

H3: Technologies for Intelligent and Secure Transportation Systems 

H4: Technologies for Safety Assurance of Embedded Circuits and Systems 

H5: Technologies for Secure Embedded Circuits and Systems 

Proposals for Tutorials and Special Sessions/Panel Discussion on the above-listed topics (but not limited to) are invited. Please check conference website for details. 

Important dates are the following: 

REGULAR PAPERS 

Abstract submission : July 19, 2015 (Sunday) 

Full Paper submission : July 26, 2015 (Sunday) 

Acceptance Notification : Sep 26, 2015 (Saturday) 

Camera-ready version : Oct 11, 2015 (Sunday) 

TUTORIALS 

Tutorial Proposals : July 19, 2015 (Sunday) 

Acceptance Notification : Sep 26, 2015 (Saturday) 

Presentation Slides : Nov 15, 2015 (Sunday) 

SPECIAL SESSIONS 

Proposal submission : July 19, 2015 (Sunday) 

General Chairs 

Pradip Bose, IBM 

Susmita Sur-Kolay, ISI 

Vice-General Chairs 

Indranil Sengupta, IITKGP 

Parthasarathi Dasgupta, IIMC 

Program Chairs 

Krishnendu Chakrabarty, Duke 

Pallab Dasgupta, IITKGP 

Partha P. Das, IITKGP 

Tutorial Chairs 

Hafizur Rahaman, IIEST 

Prabhat Mishra, UF 

Annajirao Garimella, Intel 

Publiciy chairs 

Chandan Giri, IIESTS 

Ken Stevens, U. Utah 

Monica Pereira, UFRN 

Robert Wille, U. Bremen 

Swarup Bhunia, CWRU 

T. -Y. Ho, NCKU

Intel's Skylarke Processors for PCs, Tablets and Servers

Intel is launching a full portfolio of "Skylake" processors that company officials expect will combine with Microsoft's Windows 10 operating system to help jump start a stagnant global PC market.

Executives with the chip maker for more than a year have been talking about the 14-nanometer Skylake architecture and the advanced features that are contained within it, touching on everything from graphics and imaging to security, memory, performance and wireless connectivity. In early August, Intel rolled out two Skylake chips—the Core i7-6700K and i5-6600K desktop processors—for gaming machines, and later in the month officials gave out a few more details during the Intel Developer Forum (IDF).

While Intel Corp. is going to release its code-named “Skylake” processors a little later than expected, the company keeps the plan to introduce its new micro-architecture for virtually all segments of the market continuum this year. Intel will roll-out “Skylake” central processing units for tablets, 2-in-1s, personal computers and servers this year, the chip giant confirmed this week.

“When I look at the range of what Skylake’s able to deliver from the Core M level all up to the i7 and Xeon, it’s just going to be a fantastic product,” said Intel CEO Brian Krzanich, in an interview with the IDG News Service at Mobile World Congress in Barcelona.

Intel ran into problems with production of its code-named “Broadwell” processors using 14nm manufacturing technology last year. Due to insufficient yields, the world’s largest maker of microprocessors had to delay introduction of its latest chips by about a year. However, since “Skylake” brings a lot of innovations, Intel did not want to delay it significantly. As a result, “Broadwell” products will have a relatively short lifecycle.

Intel will introduce the first “Skylake” processors in the form of dual-core Core M chips in the third quarter of this calendar year. The CPUs will power high-performance tablets, hybrid 2-in-1 personal computers and ultra-thin notebooks. It is expected that many mobile devices powered by Intel Core M “Skylake” will support Rezence wireless charging and WiGig short-range transmission technology.

In late Q3 or early Q4 the Santa Clara, California-based chip designer will introduce its first Core i3, Core i5 and Core i7 chips featuring “Skylake” micro-architecture for mainstream personal computers, including desktops and laptops. The lineup is projected to include chips with unlocked multiplier designed for enthusiast-class desktop PCs. Systems featuring the new “Skylake” processors will have improved storage performance thanks to native support of SATA Express. In addition, many “Skylake”-powered PCs will use DDR4 memory and support a variety of other innovations.

Intel also plans to introduce Xeon processors with “Skylake” cores for uniprocessor servers later this year. While there are plans to bring “Skylake” architecture to Xeon chips for dual-processor and multi-processor servers, Intel yet has to outline exact plans concerning the move.

Intel “Skylake” processors will be made using 14nm process technology and will feature a brand new micro-architecture that is designed to improve performance and power efficiency of central processing units. Unfortunately, not all “Skylake” processors will support 512-bit AVX 3.2 instructions, according to unofficial information.

Intel funding to develop printer for blind

A 13-year-old Indian-origin boy has received a huge investment from Intel for developing a low-cost printer for the blind, making him the youngest tech entrepreneur funded by a venture capital firm.

Shubham Banerjee, CEO of the Braille printer maker Braigo Labs, had closed an early round funding with Intel Capital, the company's venture capital arm, last month to develop a prototype of low-cost Braille printer.

But to attend the event, Banerjee had to take the day off from middle school. That’s because he’s just 13 years old — making him, quite possibly, the youngest recipient of venture capital in Silicon Valley history. (He’s definitely the youngest to receive an investment from Intel Capital.)

“I would like all of us to get together and help the visually impaired, because people have been taking advantage of them for a long time,” Banerjee said. “So I would like that to stop.”

By “taking advantage,” Banerjee is referring to the high price of Braille printers today, usually above $2,000. By contrast, Braigo Labs plans to bring its printer to market for less than $500.

Banerjee has invented a new technology that will facilitate this price cut. Patent applications are still pending, so he wouldn’t divulge any of the details. But the technology could also be used to create a dynamic Braille display — something that shows one line of text at a time by pushing small, physical pixels up and down, and which currently costs $6,500, according to Braigo advisor Henry Wedler, who is blind.

Banerjee also figures that volume production will help keep the price low. Currently, Braille printers cost so much because the demand is low, so current manufacturers need to set a high price in order to recoup their costs.

“The truth is that demand is low in the U.S.,” Banerjee told me. But, he added, if you brought the price low enough there would be huge demand outside the U.S.

Banerjee built the version version of his Lego Braille printer for a science fair. He didn’t know anything about Braille beforehand. In fact, he’d asked his parents how blind people read, he said onstage, and they were too busy to answer. “Go Google it,” he said they told him, so he did.

After learning about Braille, he came up with the idea to make a Braille printer. He showed it at his school’s science fair, then later entered it into the Synopsys Science & Technology Championship, where he won first prize, which included a big trophy and a $500 check.

After that, he started getting a lot of attention on his Facebook page. People kept asking him if they could buy one, he said, which led to the idea of creating a company.

Lego was just for the first prototype, by the way: Future versions will be made with more traditional materials.

So how did Intel come to invest in such a young inventor? His father, Niloy, works for Intel — but that’s not exactly how it happened, according to Niloy.

After working with the beta version of Intel Edison (the chip company’s tiny embeddable microprocessor) at a summer camp, Banerjee’s project came to the attention of Intel, which invited him to show off his printer at the Intel Developer Forum. After appearing at IDF, Intel Capital came calling.

Young Banerjee seems composed in front of crowds, which should serve him well. (That’s not surprising, given that Braigo’s website touts coverage on everything from BoingBoing and SlashGear to CNN and NPR.) When asked onstage, in front of 1,000 entrepreneurs, investors, and Intel employees, how he knew that the printer worked even though he doesn’t read Braille, Banerjee answered immediately, “I Googled it.” The crowd laughed.

“I’m happy that I live in Silicon Valley,” Banerjee said. “So many smart people.”

Do U Know? Mobile devices said to consume more energy on storage tasks

Do u know that “Flash storage takes power to write - a 20 volt jolt to each cell - but needs almost none to maintain. The real power hog is the inefficient storage software stack that eats 200 times the power required for the hardware.”

Given the always-on mobile infrastructure - background updates, instant messages, email, updates, file sync, logging and more - lots of background storage I/O is happening all the time. And it's eating your device's power budget.

Researchers from Microsoft and the University of California at San Diego benchmarked how Android and Windows RT mobile devices used energy for storing data. They focused on activities that occur with the screen off, since displays are a major power consumer when lit. "Measurements across a set of storage-intensive micro benchmarks show that storage software may consume as much as 200x more energy than storage hardware on an Android phone and a Windows RT tablet," the research team wrote in a paper. "The two biggest energy consumers are encryption and managed language environments."

Results
On Windows RT they found that the OS/CPU/DRAM overhead was between 5 and 200 times the power used by the flash storage itself, depending on how DRAM power use was allocated. File system APIs, the language environment and encryption drove the CPU power consumption during I/O. Full disk encryption - protecting user data - incurred 42 percent of CPU utilization.

On an Android phone, the encryption penalty is even worse: 2.6–5.9x more energy per KB over non-encrypted I/O.

For applications, the team found that on Windows RT, the energy overhead in a managed environment is 12.6–18.3 percent while overhead on Android is between 24.3–102.1 percent. It appears that Android's algorithms are not optimized for application I/O power efficiency.

Intel Introduces 2 Ultra-Low-Power Mobile Chips

Intel has introduced nine Core i5 and Core i7 "Haswell" mobile processors, including two ultra-low-voltage processors for Ultrabooks, the 2-gigahertz i5-4310U and the 1.5GHz 4360U. The 4360U has the company's HD 5000 graphics capability, according to Intel.

The Haswell rollout has solidified the company's dominance in the computer chip business (including what it claims are record sales of desktop Core i7 CPUs), especially on the mobile side of things. Intel is looking to further its advantage with the release of a new batch of fourth-generation Core processors designed for notebooks.

The nine new mobile Haswell CPUs are a mix of Core i5 and i7 chips that will power performance portables, though a couple are ultra-low-voltage (ULV) processors that can be used in Ultrabooks.The cheapest new one is the i5-4310M at $225 (prices will factor into the cost of a new notebook, as the laptop upgrade market is neglible); its two cores run at 2.7GHz. For about $40 more, the i5-4340M goes to 2.9GHz, while for svelte systems, there's the 2GHz i5-4310U and the 1.5GHz 4360U. Despite the slower clock speed, the 4360U costs more than the other ULV chip because it makes use of Intel's more powerful HD 5000 graphics.

Even though these are new processors, they aren't a quantum leap beyond their predecessors. Because they are clocked about 100MHz higher than the initial Haswell CPUs, that's only about a few percentage points better in performance. But who's going to argue with faster, especially when it's going to be baked into new laptops over the next few months.

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3D graphene-like material promises super electronics

Graphane, the thinnest and strongest known material in the universe and a formidable conductor of electricity and heat – gets many of its amazing properties from the fact that it occupies only two dimensions: It has length and width but no height, because it's made of a single layer of atoms. But this special characteristics sometimes makes it difficult to work with, and a challenge to manufacture.

Researchers around the world have looked for ways to take full advantage of its many desirable properties. Now scientists have discovered a material that has a similar electronic structure to graphene but can exist in three dimensions, instead of a flat sheet like graphene, could lead to faster transistors and more compact hard drives.

 Plot of energy levels of electrons in trisodium bismuthide showing that this bulk material has properties similar to graphene.

The material is called three-dimensional topological Dirac semi-metal (3DTDS) and is a form of the chemical compound sodium bismuthate, Na3Bi.

Researchers led by scientists from Oxford University, Diamond Light Source, Rutherford Appleton Laboratory, Stanford University, and Berkeley Lab's Advanced Light Source, has discovered 3DTDS.

'The 3DTDS we have found has a lot in common with graphene and is likely to be as good or even better in terms of electron mobility – a measure of both how fast and how efficiently an electron can move through a material,' said Dr Yulin Chen of Oxford University's Department of Physics.

'You can think of the electronic structure of the 3DTDS as being rather like that of the graphene – the so called ''Dirac cone'' where electrons collectively act as if they forget their mass – but instead of flowing masslessly within a single sheet of atoms, the electrons in a 3DTDS flow masslessly along all directions in the bulk.'

Moreover, unlike in graphene, electrons on the surface of the 3DTDS remember their 'spin' – a quantum property akin to the orientation of a tiny magnet that can be used to store and read data – so that the magnet information can be directly transferred by the electric current, which could enable faster and more efficient spintronic devices.

'An important property of this new type of material is its magnetoresistance – how its electrical resistance changes when a magnetic field is applied,' said Dr Chen. 'In typical Giant Magnetoresistance Materials (GMR) the resistance changes by a few tens of percent and then saturate but with 3DTDS it changes 100s or 1000s of percent without showing saturation with the external magnetic field. With this much larger effect we could make a hard drive that is higher intensity, higher speed, and lower energy consumption – for example turning a 1 terabyte hard drive into a drive that can store 10 terabytes within the same volume.'

While this particular compound is too unstable to use in devices, the team is testing more stable compounds and looking for ways to tailor them for applications.

Dr Chen said: 'Now that we have proved that this kind of material exists, and that such compounds can have one of the highest electron mobilities of any material so far discovered, the race is on to find more such materials and their applications, as well as other materials with unusual topology in their electronic structure.'

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India's fab project fails to attract big chip players

Two consortia, led by Hindustan Semiconductor Manufacturing Corp. and Jaypee Associates, remain the top contenders to construct and equip proposed wafer fabrication facilities in India. No large semiconductors manufacturers have emerged as leaders for the project. HSMC is working with STMicroelectronics and Silterra, while Jaypee is collaborating with IBM Microelectronics and Tower Semiconductor.

Under the current proposals, Jaypee has tied up with IBM and Tower Jazz and has proposed a facility in Greater Noida with an investment of Rs 26,300 crore, while HSMC has partnered with ST Microelectronics and Silterra and has planned its unit at Prantij near Gandhinagar in Gujarat with an investment of Rs 25,250 crore.

India is trying to create an electronics manufacturing ecosystem to prevent the loss of billions of dollars of foreign exchange in such imports every year. This bill, expected to reach $55 billion (aboutRs 3.4 lakh crore) by 2020 from about $7 billion (Rs 43,600 crore) now, is projected to outstrip oil imports, according to a report commissioned by the industry lobby India Electronics and Semiconductor Association last year.

According to two government officials, the Department of Electronics and Information Technology (DeitY) has received only two new proposals - one by Interactivity Group (supported by a group of IIT alumni) and another by APSTL, an Arizona-headquartered technology firm. Even though an empowered committee set up to evaluate all the proposals is still studying them, an official said it is unlikely something concrete will come out of the two new applications.

With the government's support for setting up the fab firming up at about 40 per cent of the total cost, officials were keen on figuring out if other chipmakers could also be enticed to show interest.

Typically, setting up a chip foundry costs around $4-5 billion (Rs 24,800-31,000 crore). "The idea was, with the incentives firmed up, could we push the fence-sitters off the fence, but that didn't happen," the industry executive said. The deadline to submit initial plans in the fab under a separate call for expressions of interest ran out in November, and there have been no new viable plans submitted other than the two the government had already approved in-principle.

However, a lack of interest the second time around as well underlines the concerns about the feasibility of setting up fab units in the country. Experts argue the long-gestation period and the technology mandates of the government may diminish the usefulness of the projects when they finally come up. The facilities are expected to start production only sometime in 2017.

Broadcom releases satellite-constellation location IC

Broadcom Corporation has introduced a Global Navigation Satellite System (GNSS) chip, designated BCM47531, that generates positioning data from five satellite constellations simultaneously (GPS, GLONASS, QZSS, SBAS and BeiDou), totaling 88 satellites. The newly added Chinese BeiDou constellation increases the number of satellites available to a smartphone, enhancing navigation accuracy, particularly in urban settings where buildings and obstructions can cause interference.

The company’s new GNSS SoC is based on its widely deployed architecture that reduces the “time to first fix” (TTFF) and allows smartphones to quickly establish location and rapidly deliver mapping data. The SoC also features a tri-band tuner that enables smartphones to receive signals from all major navigation bands (GPS, GLONASS, QZSS, SBAS, and BeiDou) simultaneously.

The BCM47531 platform is available with Broadcom’s Location Based Services (LBS) technology that delivers satellite assistance data to the device and provides an initial fix time within seconds, instead of the minutes that may be required to receive orbit data from the satellites themselves.

The BCM47531 brings a number of powerful features to the table:

• Simultaneous support of five constellations (GPS, GLONASS, QZSS,SBAS and BeiDou) allows for position calculations based on measurements from any of 88 satellites.
• Broadcom's tri-band tuner brings the ability to receive all navigation bands, GPS (which includes QZSS and SBAS), GLONASS and BeiDou simultaneously to the commercial GNSS market without having to reconfigure and hop between bands.
• Utilizes BeiDou signals for up to 2x improved positioning accuracy.
• Best-in-class Assisted GNSS (AGNSS) data available worldwide from Broadcom's hosted reference network.
• Allows a device to interchangeably use the best signal from any satellite regardless of the constellation, ensuring better accuracy in urban and mountainous environments.
• Features advanced digital signal processing for interference rejection that enables satellite signal search and tracking during LTE transmission.
• Leverages Broadcom's connectivity solutions including Wi-Fi, Bluetooth Smart, Near Field Communications (NFC), Instant Messaging System (IMES) and handset inertial sensor data for best indoor/outdoor location.

China used more than half of world's ICs in 2012

China's semiconductor use has hit a record high and accounts for more than half of the global market, but the country is overly dependent on foreign suppliers for relevant products, according to a PricewaterhouseCoopers report issued on Thursday.

With an 8.7 percent growth in 2012, China's semiconductor use was 52.5 percent of the total worldwide, said a PwC report titled China's Impact on the Semiconductor Industry - 2013 Update. Semiconductors act as an engine now driving an increasing amount of the technology in people's lives.

The growth in Chinese semiconductor use is a remarkable contrast to the global market for semiconductors, which experienced an overall decline of3 percent in 2012, the report said.

China is expected to continue its domination of semiconductor purchasing in the foreseeable future with its market share possibly reaching 60 percent by 2017,Raman Chitkara, PwC's global technology and semiconductor leader, said in an interview with China Daily.

"One of the major reasons why China has grown so big in semiconductor consumption is that the country isrising to become the world's capital of electronic manufacturing," Chitkara said.

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India Plans To Build 2 Wafer Fabs

The government of India on Thursday approved "in principle" a plan to construct and equip two wafer fabrication facilities in the country, in a move designed to reduce India's reliance on imported semiconductors. Two consortia will go ahead with the twin fab projects. One is led by STMicroelectronics, an integrated device manufacturer, and the other is spearheaded by Tower Semiconductor, a silicon foundry. These companies will add their names to list of VLSI companies in India and boost the manufacturing capability.

"The Cabinet has given in-principle approval for setting up of semiconductor wafer fabrication manufacturing facilities," Information and Broadcasting Minister Manish Tewari told reporters after a meeting of the Union Cabinet, chaired by Prime Minister Manmohan Singh.

After considering proposals from two consortia, the government took the decision. The government received proposals from two consortiums to set up chip fabrication units in the country. One was led by Israel's Tower Jazz and the other was led by Geneva–based chipmaker STMicroelectronics.

Israel-based foundry chipmaker Tower Semiconductor Ltd, which operates under the brand name TowerJazz, partnered with IBM and Indian infrastructure conglomerate Jaypee Associates to build and operate a 300mm chip facility in India. On the other hand, STMicroelectronics partnered with Hindustan Semiconductor Manufacturing Corp. (HSMC).

Welcoming the government's decision, India Electronics & Semiconductor Association (IESA) President PVG Menon said, "The IESA deems the fab a highly strategic game changer for India. Some of the world's leading economies including the USA, France, Germany, Ireland, Japan, Singapore, Taiwan and China besides a number of developing economies like Malaysia and Israel have their own fabs. These fabs continue to contribute significantly to the growth and development of the economy of their respective countries and we hope that this would be the case in India as well."

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Cisco’s nPower chips for moving data at 400 Gbps

Semiconductors continue to advance, as a slew of announcements by Intel and Apple’s new A7 processor showed this week. But don’t forget about Cisco Systems.

The biggest provider of routing and switching systems has long retained the capability to design specialized processors for its hardware, as well as turn to off-the-shelf chips from commercial suppliers where that makes the most sense. Now Cisco designers have come up with another singular piece of home-grown silicon.

It’s a new product line called the nPower, and Cisco says the chips can pump as much as 400 gigabits of data per second. By contrast, the company’s prior technology could handle 140 gigabits and required more than one chip, Cisco says. The new capacity translates into hundreds of millions of transactions per second.

To what end? Of course, computer and smartphone users will continue to watch more YouTube videos and the like. But Surya Panditi, Cisco’s senior vice president and general manager of engineering, says a key driver for the technology is a coming change in the nature of network traffic.

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Android Kitkat

 Google recently announced its latest version of Android - 4.3 Jelly Bean, which turned out to be nothing to write home about. Ever since then, the next iteration of Android OS has taken the spotlight and has been the talk of the town.

Just when all of us thought that Android 5.0 Key Lime Pie would be the next upcoming version of the Android OS, Google has announced that the successor of the Android 4.3 Jelly Bean would be named KitKat (yeah, the brand) and it is Android 4.4, not 5.0 as rumored before.

Sundar Pichai, the Android and Chrome head has confirmed the naming scheme of the next version of Android. Android 4.4 KitKat is named after Neslte's popular candy bar, which is trademarked and licensed by Hershey in the US.

Google also says that "it's our goal with Android KitKat to make an amazing Android experience available for everybody". The bold statement also suggests that Google plans to make use of its next iteration of Android in smart watches, gaming consoles and other electronic gadgets.

Here's the list of past Android versions with the dessert naming scheme:

Android 1.5: Cupcake

Android 1.6: Donut

Android 2.0: Eclair

Android 2.2: Froyo

Android 2.3: Gingerbread

Android 3.0: Honeycomb

Android 4.0: Ice Cream Sandwich

Android 4.1: Jelly Bean

Android 4.2: Jelly Bean

Android 4.3: Jelly Bean

Android 4.4: KitKat

 

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Microsoft To Acquire Nokia's Devices And Services

Nokia, once a world leader in the mobile phone market, has had a tough few years and attempts by the company to join in on the smartphone explosion did not go well.

Nokia has seem somewhat of a resurgence lately with a series of high quality smartphones on the Windows Phone platform. Many of the phones such as the Lumia 928, 928 and 1020 with it's 41 megapixel are excellent devices and offer a real choice for anyone wanting to escape the ecosystems of Apple and Android. In fact the majority of users who actually try their Windows Phones quickly find that they enjoy the very different experience they have had with their previous smartphones. The problem for Nokia and Microsoft was getting users to even think about separating from their iPhone or Android device. 

According to the companies' press releases, 32,000 people will transfer across Microsoft, including 4,700 people in Finland and 18,300 employees directly involved in product manufacture. If you thought it was only the Windows Phone component of the phone business, you'd be wrong: Microsoft will also take into ownership Nokia's Asha range of feature phones. Patent-wise, Microsoft gets 10-year non-exclusive license to its Finnish partner's library of ideas and "reciprocal rights" to use Microsoft patents within its HERE mapping services. While Microsoft will be able to use the Nokia branding on its products, the Finnish company will now focus on its mapping, infrastructure and advanced tech arms.

In 2011, after writing a memo that said Nokia lacked the in-house technology and needed to jump off a "burning platform", Elop made the controversial decision to use Microsoft's Windows Phone for smartphones, rather than Nokia's own software or Google's (GOOG.O) ubiquitous Android operating system.

The deal will see Microsoft taking full control over Nokia's Smart Devices and Mobile Phones business units, which produce the Lumia family of smartphones and low-cost featurephones respectively. Nokia, meanwhile, retains its telecommunications hardware business Nokia Siemens Networks, Here location-based services arm, and its patent portfolio under the Advanced Technologies division. These patents are to be licensed to Microsoft for at least a ten-year period, the agreement states.

The acquisition will truly allow  Microsoft to enter the market in direct competition with its Windows Phone licensees. It's a move that was first telegraphed by the launch of the Surface family, which put the company in direct competition with third part manufacturer's in the Windows 8 and Windows RT tablet markets.
Nokia first started producing phones back in 1996 and for many years they were one of main innovators of smartphones. Of course the release of the iPhone in 2007 and the emergence of Android devices began to strangle Nokia. During the past couple of years Microsoft has provided a kind of life boat to Nokia with their Windows Phones and now it looks like Microsoft has taken over the reins entirely.
Time will tell for both Nokia and Microsoft, but at this very early point I believe it is a good move for both companies and consumers.

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NVIDIA Sets Up New Tech Center Near Detroit

The new Nvidia Technology Center in Ann Arbor, Mich., will focus on working the IC design company's chips into automotive electronics. While Nvidia made a name for itself with its graphics technologies, the last few years have seen a shift at the company as its watches its Tegra system-on-chip (SoC) division grow."Our new facility will help our growing team of Michigan-based engineers and executives work with automakers and suppliers to develop next-generation infotainment, navigation and driver assistance programs," Nvidia's Danny Shapiro said.

Even with such successes, the automotive industry is still a small part of Nvidia's overall business - but the new technology centre looks to shift that balance. Located in Michigan, a short distance from infamous car-centric Detroit, the centre will concentrate on building technologies specifically for the automotive industry.

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Motorola touts the power of 8 cores in new phone SoC

Motorola Mobility has designed an eight-core system-on-a-chip device, the Motorola X8 Mobile Computing System, to be used in its Droid mobile handsets. The SoC features a dual-core application processor, four cores for graphics, one for "contextual computing" and the eighth for "natural language processing," according to the Google subsidiary. Motorola declined to identify the silicon foundry making the chip.

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