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Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
Monday, 21 September 2015
SVEditor - A SystemVerilog Editor Eclipse Plugin
Tuesday, 24 July 2012
Editing your FPGA source
I noted that in a recent poll of FPGA developers, emacs was far and away the most popular VHDL and Verilog editor. There are a few reasons for this – namely, emacs comes with packages for editing your HDL of choice. For those of us not wanting to install (and learn) the emacs operating system, I got Notepad++ to work with these packages.
Notepad++ already has VHDL and Verilog highlighting along with other advanced text editor features, but I wanted templates, automated declarations and beautification. To do this, he used the FingerText to store code as snippets and call them up at the wave of a finger.
As I writes his code, the component declarations constantly need to be updated, and with the help of a Perl script I can update them with the click of a hotkey. Beautification is a harder nut to crack, as Notepad++ doesn’t even have a VHDL or Verilog beautifier plugin. This was accomplished by installing emacs and running the beautification process as a batch script. Nobody can have it all, but we’re thinking that this method of getting away from emacs is pretty neat.
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This is in continuation of our previous post on Low Power Design Techniques , where we learned about different types of strategies used to...
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Static timing analysis verifies circuit timing by “ adding up propagation delays along paths between clocked elements ” in a circuit. It c...
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Formal Definition An interface constant declared in the block header of a block statement, a component declaration, or an entity declaratio...
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Formal Definition Delays can be specified for minimum, typical, and maximum propagation times. Simplified Syntax # (min:typ:max) # (min:t...
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Definition: The action of a wait statement when the conditions for which the wait statement is waiting are satisfied. Description A susp...