- Front end RTL/Testbench code compilation and simulation flows
- Automation of running tests in regressions, generating reports, analyzing failures, debug automation
- Connectivity checks, netlist parsing, automatic generation/modification any RTL module/stubs, etc
- Synthesis, P&R tools interfacing, and back end flow.
- Several project management utilities - regression pass rates, trends, bug charts, etc - that helps in tracking projects
- Any other task that is repetitive in workflow and can be automated.
Featured post
Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
Thursday, 6 August 2020
Use of Scripting languages in VLSI
Monday, 21 November 2016
Advantages of Python over Perl
Wednesday, 19 September 2012
Programming FPGAs with Python
For everyone who wants to get started with developing for FPGA’s and dont want to waste time in learning a new programming language or they just want to use their current knowledge of programming with Python to program an FPGA, this tool is just made for you!
The Python Hardware Processsor is written in Myhdl which makes it possible to run a very small subset of python on an FPGA, it converts a very simple Python code into either VHDL or Verilog and then a hardware description can be uploaded to the FPGA:
“Due to the python nature of Myhdl and the Python Hardware Prozessor written with it, it allows you, to write a Programm for the prozessor, to simulate the Hardware Processor and to convert the Processor to a valid hardware description (VHDL or Verilog) inside a single python environment.”
MyHDL surely won’t replace VHDL or Verilog but it could be a great tool for simulation and to test the behavior of your design and it’s certainly a tool worth looking into if you want to jump into the world of FPGAs.
Feel free to discuss in the comments thread.
-
There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “...
-
When ModelSim is automatically lunched within the ISE environment it just displays the top entity level signals in the Wave View window. Ho...
-
String data type is used for storing strings, the size is dynamic and string data types come with build in methods. If you have ever tried...
-
One of our colleagues always had to struggle with the Verilog / SystemVerilog syntax. Whenever he opens a .sv file he needs to set the synta...
-
Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verify...





