- Front end RTL/Testbench code compilation and simulation flows
- Automation of running tests in regressions, generating reports, analyzing failures, debug automation
- Connectivity checks, netlist parsing, automatic generation/modification any RTL module/stubs, etc
- Synthesis, P&R tools interfacing, and back end flow.
- Several project management utilities - regression pass rates, trends, bug charts, etc - that helps in tracking projects
- Any other task that is repetitive in workflow and can be automated.
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Programming FPGAs with Python
For everyone who wants to get started with developing for FPGA’s and dont want to waste time in learning a new programming language or they just want to use their current knowledge of programming with Python to program an FPGA, this tool is just made for you!
The Python Hardware Processsor is written in Myhdl which makes it possible to run a very small subset of python on an FPGA, it converts a very simple Python code into either VHDL or Verilog and then a hardware description can be uploaded to the FPGA:
“Due to the python nature of Myhdl and the Python Hardware Prozessor written with it, it allows you, to write a Programm for the prozessor, to simulate the Hardware Processor and to convert the Processor to a valid hardware description (VHDL or Verilog) inside a single python environment.”
MyHDL surely won’t replace VHDL or Verilog but it could be a great tool for simulation and to test the behavior of your design and it’s certainly a tool worth looking into if you want to jump into the world of FPGAs.
Feel free to discuss in the comments thread.
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