VHDL code for AND gate

 

library ieee;
use ieee.std_logic_1164.all;

entity my_and is

  port (a, b : in  std_logic;
        c    : out std_logic);

end my_and;

architecture my_and_arc of my_and is

  begin
  c <= a and b;

end my_and_arc;

Positive and Negative Edge Detector Circuit

Positive and negative edge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered events on certain GPIO inputs. Here i will show you a simple circuit which is use to detect Positive as well negative edges.

VHDL CODE : 

library ieee;
use ieee.std_logic_1164.all;
entity edge is
   port (
    inp        : in  std_logic;         -- inpit
    clk        : in  std_logic;         -- clock
    rst        : in  std_logic;         -- reset
    edge_op : out std_logic);        -- setected edge output
 end edge;

architecture edge_ar of edge is
  signal sig1 : std_logic;              -- signal from 1st flop
  signal sig2 : std_logic;              -- signal from 2nd flop

begin  -- edge_ar
   edge : process(clk, rst)
  begin
    if rst = '1' then
      sig1 <= '0';
      sig2 <= '0';
    elsif clk'event and clk = '1' then
      sig1 <= inp;
      sig2 <= sig1;
    end if;
  end process edge;

  edge_op <= sig1 xor sig2;

end edge_ar;

What is Clock Skew?

Given two sequentially-adjacent registers, Ri and Rj, and an equipotential clock distribution network, the clock skew between these two registers is defined as

Tskew-i,j = Tci - Tcj

where Tci and Tcj are the clock delays from the clock source to the registers Ri and Rj, respectively.

ASIC Implementation Design Cycle

Following diagram shows the basic flow of the complete HDL Implementation design cycle.

FPGA Implementation Design Cycle

Following diagram shows the basic flow of the complete HDL Implementation design cycle.

Netgen - The Circuit Netlist Comparison (LVS) and Netlist Conversion Tool

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Netgen version 1.3 is the stable branch and has been essentially unchanged for several years. The development branch version 1.4 is an attempt to bring netgen up to par with the industry-standard Calibre tool from Mentor Graphics. Since (as far as I know) all LVS tools are based on the same class partitioning algorithm, this effort is not as difficult as it may seem. Mostly, netgen must be made to properly understand hierarchy, device properties, and generate a more readable output. All these changes are now underway (as of November 2007, when the development version 1.4 branch was created).

Netgen was developed independently of magic, written by Massimo Sivilotti, and eventually incorporated into the beginnings of the Tanner L-Edit suite of tools. However, the original code was left open source, and so I have incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.

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IRSIM - tThe Switch-level Digital Circuit Simulator.

IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

IRSIM shares a history with magic, although it is an independent program. Magic was designed to produce, and IRSIM to read, the ".sim" file format, which is largely unused outside of these two programs. IRSIM was developed at Stanford, while Magic was developed at Berkeley. Parts of Magic were developed especially for use with IRSIM, allowing IRSIM to run a simulation in the "background" (i.e., a forked process communicating through a pipe), while displaying information about the values of signals directly on the VLSI layout.

For "quick" simulations of digital circuits, IRSIM is still quite useful for confirming basic operation of digital circuit layouts. The addition of scheduling commands ("at", "every", "when", and "whenever") put IRSIM into the same class as Verilog simulators. It is, in my opinion, much easier to write complicated testbench simulations using Tcl and IRSIM. I have used IRSIM to validate the digital parts of several production chips at MultiGiG, including the simulation of analog behavior such as PLL locking.

IRSIM version 9.5 was a long-standing and stable version that corresponded to the relatively stable Magic version 6.5. When magic was recast in a Tcl/Tk interpreter framework (versions 7.2 and 7.3), IRSIM could no longer operate as a background process. However, it was clear that if IRSIM could also be recast in the same Tcl/Tk interpreter framework, the level of interaction between it and Magic would be greatly increased.

I set about to create the "new" IRSIM, although it came along in fits and starts as I had time to work on it. Because the original "analyzer" graphic display window (and GUI, to a very limited extent) was written in Xt (the rather primitive window system that is an integral part of X11), it was scrapped for a while. In its place, I substituted graphs in "Blt" based on the same in "tclspice" (see SourceForge for the tclspice project). Unfortunately, "Blt" insists that all data vectors must be real-valued, which is 1) a severe waste of space for binary digital values, and 2) is unable to represent the concept of an "unknown" value that is so crucial to fast switch simulation. So, eventually I was forced to scrap BLT and actually sit down and code out a real Tcl-based analyzer window and GUI. The result is finally done in revision 9.7.3.

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