Clock Skew In Sequential Circuits

Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design principle that timing must satisfy register setup and hold time requirements. Both data propagation delay and clock skew are parts of these calculations. Clocking sequentially-adjacent registers on the same edge of a high-skew clock can potentially cause timing violations or even functional failures.

Below Figure 1 shows an example of sequentially-adjacent registers, where a local routing resource has been used to route the clock signal. In this situation, a noticeable clock skew is likely.

In Figure 1, all registers are clocked at the same edge, but the arrival time of the edge is different at each register. Figure 2 indicates an example of the clock skew for the circuit shown in Figure 1.

Figure 1: Sequentially Adjacent Registers with Clock Skew

Figure 2: Clock Arrival Time Functions in the Circuit of Figure 1

What is Clock Skew?

Given two sequentially-adjacent registers, Ri and Rj, and an equipotential clock distribution network, the clock skew between these two registers is defined as

Tskew-i,j = Tci - Tcj

where Tci and Tcj are the clock delays from the clock source to the registers Ri and Rj, respectively.