VLSI Interview Questions-1

1. what is the difference between mealy and moore state-machines
2. how to solve setup and hold violations in the design
3. what is antenna violation & ways to prevent it
4. we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
5. what is tie-high and tie-low cells and where it is used
6. what is the difference between latches and flip-flops based designs
7. what is High-Vt and Low Vt cells
8. what is LEF mean?
9. what is DEF mean?
10. steps involved in designing an optimal padring
11. what is metastability and steps to prevent it
12. what is local-skew, global skew and useful skew
13. what are the various timing-paths which i should take care in my STA runs?
14. what are the various components of leakage-power
15. what are the various yield losses in the design
16. what is meant by virtual clock definition and why do i need it
17. what are the various variations which impacts timing of the design
18. what are the various Design constraints used, while performing synthesis for a design
19. specify few verilog constructs which are not supported by the synthesis tool
20. what are the various capacitances with an MOSFET?
21. Vds-Ids curve for an MOSFET, with increasing Vgs
22. explain basic operation of an MOSFET
23. what is channel length modulation
24. what is body effect
25. what is latchup in CMOS design and ways to prevent it?
26. what are the various design changes you do to meet design power targets
27. what is meant by library characterization
28. what is meant by wireload model
29. what are the measures to be taken to design for optimized area
30. what all will you be thinking while performing floorplan
31. what are the measures in the design taken for meeting signal integrity targets
32. what are the measures taken in the Design achieving better yield
33. what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
34. what are the steps incorporated for Engineering Change order[ECO]
35. what are the steps performed to achieve Lithography friendly Design
36. what does synthesis mean?
37. what are the pre-requistes to perform synthesis
38. can you explain the synthesis flow
39. what are the various ways to reduce clock insertion delay in the design
40. what are the various functional verification methodologies
41. what does formal verification mean
42. how will you time the output path in STA
43. how will you time the input path in STA
44. what is false path mean in STA and in what scenarios falsepath can come
45. what does multicycle path mean in STA and in what scenarios MCP can come
46. what are source synchronous paths in STA
47. Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it.
48. we have multiple instances in RTL, do you do anything special during synthesis stage
49. what do you call an event and when do you call an assertion.
50. what is difference between FPGA and ASIC.

Solutions to these questions will be provided on request.

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