What Is A 'Clocking Block'?

In Verilog, a module is the unit for any design entity. SystemVerilog extends this to include other design entities such as an interface, a program block and, last but not the least, a clocking block. An interface separates how a design interacts with the rest of the design from the design itself. A program block separates a test benching function from a silicon implementable design. And a clocking block specifies clock signals and the timing and synchronization requirements of various blocks. A clocking block is helpful in separating clocking activities of a design from its data assignments activities and can be used powerfully in test benching.

A clocking block assembles all the signals that are sampled or synchronized by a common clock and define their timing behaviors with respect to the clock. It is defined by a clocking-endclocking keyword pair. Perhaps an example will describe this best.

clocking clock1 @(posedge clk1);
   default input #2ns output #3ns;
   input a1, a2;
   output b1;
endclocking
In the above example,

1. The name of the clocking block is clock1. You can have as many clocking blocks in your environment as you want. Also, there may be multiple clocking blocks for the same clock, inputs or outputs in a single design.
2. The clock associated with this clocking block is clk1. Each clocking block must have at least one clock associated with it.
3. The default keyword defines the default skew for inputs (2 ns) and output (3 ns).
4. The input and output keywords define the input and output signals associated with the clock and the skew defined earlier.
5. One thing to note here is that input or output declarations inside a clocking module does not specify the data width.

A clocking block is both a declaration and an instance of that declaration and can only occur within a module, interface or program block (in the same scope as an always block). Variables inside a clocking block can be accessed specifying the full pathname. For instance, if the full pathname for clock1 above is top.test.clock1, the full pathname for variable a1 is top.test.clock1.a1.

A clocking block only describes how the inputs and outputs are sampled and synchronized. It does not assign a value to a variable. That is left to a module, interface or program that the clocking module is part of. While the parent block of a clocking module properly assigns a value to a variable, a clocking block defines how inputs are sampled and outputs are synchronized for its parent module. This is why an input or output declaration inside a clocking block does not need to specify any data width since it is only relevant if you assign a value to a variable or read from it.

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VLSI Interview Questions - 2

• What is the frequency of the DDR / voltage
• What is the memory size ; explain prefetch in memory context
• What is the Bit length for data
• Basic protocol level DDR knowledge
• What is absolute jitter
• What are the types of jitter you know
• How do you make power measurements
• Asynchronous reset flip flop / Synchronous reset flip flop difference
• What is a asynchronous reset D flip flop
• How do you double the clock frequency using combinational logic
• What do you understand by synthesis
• What is the basic difference between ASIC and FPGA design flow
• Blocking and non-blocking statements
• Tools used for front end
• PCI clock frequency
• What is metastability
• Delay parameters which matter for DDR ( cas latency what do u know about it )
• RAS / CAS
• Master – Slave FF
• Add delay on FF1-FF2 D1Q-D2 path  and analyze a circuit ( a double inverter)
• Swap the delay onto the clock line and analyze the circuit ( double inverter )
• Delay nos. given 20 ns (double inverter) on clock skew line, 5 ns on the first FF to second FF line ; 100 ns clock period – analyze the circuit
• 4:1 mux from 2:1 mux ABCD in order – draw truth table and prove
• A equality comparator design – make it an inverter
• XOR gate from NAND gate
• Explain DDR protocol and timing
• Ethernet packet format
• Test setup and explain settings
• Two critical debug you have done in your career and lessons learnt
• Decoder design – explain address decoder how it works given x number of rows and columns draw timing and circuit
• 8085 block diagram ( general uP concepts)
• DRAM
• FF can be used in memory? Why / why not ?  FF vs DRAM
• Five skills obtained from board design / rules – best practices
• Latch vs FF
• VHDL code snippet
• SR FF.
• DDR banks
• 100 MHz clock is used to give input – need to send out data at 200 MHz suggest circuits for this
• DDR explanation – chip level
• 100 MHz in from 1 PLL clock / 100 MHz out from PLL2 clock – design circuit
• What problems will come in case (q 20 / 22)
• FIFO design details and problems
• some more design problems were asked to be analyzed
• What is set up time
• What is hold time
• ASIC Design flow
• Challenges in ASIC Design
• Latch and Flip-Flop
• Design a simple circuit for motion detector
• Use of a decoder
• Types of Flip Flop
• Which is the most common flip flop used in ASIC designs
• FF --- Combinational Logic --- FF ( Analysis of standard circuit)
• Analysis of circuit with delays ( buffers added to clock lines)
• How to find the maximum clock frequency of a given circuit
• Synthesis tools and styles
• Timing constraints to be given for ASIC design
• What happens when you decrease the clock frequency – does setup / hold time violations at say 300MHz frequency vanish at 3 MHz
• What all influence the delay of an element ( Flop – capacitance ?)
• What parameters influence delay ( temperature effect on delay)
• If input transition is faster what happens to delay of a cell
• What do you understand by drive strength
• High drive of a cell – correlates to what ?
• Importance of hold time (adder can become subtractor – Function change!!)
• How to solve set-up time violations
• How to solve hold time violations
• What is PRBS
• What is the difference between single ended and differential
• Why is PRBS needed in a tester
• USB protocol / packet level understanding? Basics explanation
• 80 MHz DDR – what do you understand from this
• SDR and DDR difference and advantages
• Test setup
• Triplexer – why passive optical networks what it means
• WDM – CO – CPE
• What do you understand by a Loopback why is it needed
• Challenges in finding maximum clock frequency in ASIC design
• Power estimation in chips ?
• Why is place and route important – any understanding of the same
• What is skew – clock skew
• What is slew – slew rate
• Why do you want to do verification and enter ASIC domain
• What is jitter
• What is cycle – cycle / period jitter. How is it estimated
• Common i/fs in a system
• Pulse width
• Why is setup and hold time first needed
• Effect of temperature on delays ( delay increases with temperature)
• Why clock skew arises
• What is positive and negative skew
• Is positive skew and advantage or disadvantage – how does it help
• What is the worst pattern that can be used to test a set of lines
• SSN – crosstalk
• what do you actually look for in SI
• What do you do in a bring-up
• What is Custom and Semi-Custom ASIC design
• ASIC – FPGA difference ( low power is a key)
• When a Flop is used; when a latch is used and why?
• Why random patterns?
• DFM?
• Clock tree routing problems
• Models for components
• Buffer circuit in IOs – Pulse width distortion / duty cycle distortion why it happens performance before and after pads causes for degradation
• Can you explain a general verification methodology flow 
• Explain your verification architecture 
• Why do you think we need functional coverage 
• Can you explain e-manager coverage implementation methods you have used 
• DDR + problems you faced in bring up 
• Can you give me an FSM/code/circuit to implemet code for following waveform 
• 32 bit addr / 32 bit data / size -- map to 64 bit memory - give structure / how will you sample data for byte, word, half word, dword accesses 
• You have 256 MB sys memory - (insufficient say for ur huge ASIC) how will u verify 
• Dynamic memory 
• List and indexed lists 
• Can you explain some RISC processor architecture you know 
• RISC vs CISC you know from college 
• How can specman handle semaphores 
• Some addressing fundamentals
• Multiple threads in your env - what did you implement to run three cores simultaneously. 
• AXI - addressing ; 4k page boundary cross over fetches; wrapping concept ; Multiple slave out of order transaction support - waveforms as to how these transactions will be ; size / length concepts

What is Synthesis?

Synthesis is the stage in the design flow which is concerned with translating your VHDL code into gates - and that's putting it very simply! First of all, the VHDL must be written in a particular way for the target technology that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Are there any VHDL source code libraries available to save me having to re-invent common code fragments and functions?

There are a few libraries available for most levels of VHDL design. The IEEE library contains very low-level type-and-function packages. The std_logic_1164 package is an industry standard, and practically every piece of VHDL you ever write will use this package; the types std_logic and std_logic_vector are the overwhelmingly dominant types for anything related to digital design. For arithmetic, numeric_std (from the same IEEE library) is a collection of functions that work on std_logic and its derivatives. For other libraries of components, have a look in the comp.lang.vhdl FAQ.

I've heard that VHDL is very inefficient for FPGAs. Is that true?

It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.

I can see how to write abstract behavioural descriptions in VHDL, but how do you describe and simulate the actual hardware?

This is probably the biggest hurdle that many hardware engineers face when moving to VHDL. After all, sometimes we need to be able to describe actual implementation as well as abstract functionality. The way to describe "physical" hardware in VHDL is to write VHDL models of those components. This is supported in VHDL through the use of instantiation. VHDL does not allow you to physically simulate your hardware. You can only simulate a model of that component in a VHDL simulation.

Historically, gate-level simulation using VHDL has been notoriously slow. This led to the creation of the 1076.4 working group to provide a mechanism to allow faster gate-level simulation using VHDL. Their effort became known as the VITAL standard. VITAL is not a VHDL issue for you, but an EDA vendor/ASIC supplier issue. A simulator is VITAL compliant if it implements the VITAL package in its kernel (this is faster than simulating the VITAL primitives in the VITAL package). You don't need to change your VHDL netlist; your ASIC vendor needs to have a VITAL compliant library though, in order for you to take advantage of the simulation speed up. Thus the ASIC vendor's library elements need to be implemented entirely in VITAL primitives. Note that many companies use Verilog for gate-level simulations as it is still faster than VHDL, even with the improvements from VITAL. The reason is that Verilog was designed from the start as a gate-level simulation language.

Can you give me a measure of the productivity improvements I should expect from VHDL?

Well, do you believe the hype! Yes, ultimately there are considerable productivity gains to be had from using high-level design techniques in conjunction with synthesis technology, providing that your designs are: complex, amenable to synthesis, not dependent upon the benefits of a particular technology.

Obviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let's face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into HLD. Of course, once you are benefiting from HLD productivity gains, the specification phase becomes more significant. OK, that's HLD: VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process. However, you won't get those benefits immediately. Your first VHDL-based project will probably take slightly longer than if you had used your previous design process.

Are there any tools to generate VHDL test benches automatically?

The basic answer is no. Writing a testbench can be a complex task, and can be more complex than the design being tested. If you mean "Can I get a code framework for a simple testbench", then a number of tools provide simple "testbench templates"; even the Emacs editor VHDL mode can do this! For more advanced ways of writing testbenches, you might want to look at the so-called "Testbench Automation" tools, such as SystemVerilog, SystemC Verification Library, Cadence Specman, and Synopys Vera. These tools involve learning another language of course. If you want to know how to write more complex testbenches (for instance to cope with data arriving in a different order from the order it entered a device).

A VHDL design can be moved to any tool or technology. Right?

On the face of it, this is true. VHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may have broad agreement of what constitutes synthesizable code, but may interpret that code in different ways.

Is VHDL going to be developed further?

You might have heard a lot about System Verilog, and wondered if VHDL is going to also be developed? There is an activity to develop an improved VHDL, and VHDL-2008 was released in January 2009. This might help engineers to write efficient code in VHDL.

How many versions of VHDL are there?

There are four. The original release of the VHDL language occurred in 1987 with the adoption of the Language Reference Manual as an IEEE standard. In 1993, the IEEE-1076 standard was modified and ratified and became known as VHDL'93. This is now widely supported. In 2000, the VHDL 1076 2000 Edition appeared - this fixed shared variables by introducing the idea of protected types. Finally, VHDL 1076-2002 appeared. This includes protected mode types, but also changes ports of mode buffer to make them more usable, along with some other small changes. In practice, VHDL 1076-1993 is the current flavor of VHDL which is widely supported by tool vendors.

How must I write VHDL to make it synthesizable?

Because large parts of the language make no sense in a hardware context, synthesizable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simply but important fact will only lead to pain later.

Can I use VHDL for the analog part of a design?

Yes and No. Yes, there is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL 93, which allows modeling of both analogue and digital in the same language. However the idea of analogue synthesis is still in its early days, so currently you wouldn't normally be able to go on and synthesize an analogue model written in VHDL-AMS. There's a VHDL-AMS website at www.eda.org/vhdl-ams.

What is the difference between VHDL and Verilog?

Fundamentally speaking, not a lot. You can produce robust designs and comprehensive test environments with both languages, for both ASIC and FPGA. However, the two languages approach the task from different directions; VHDL, intended as a specification language, is very exact in its nature and hence very verbose. Verilog, intended as a simulation language, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs. VHDL doesn't let you get away with much; Verilog assumes that whatever you wrote was exactly what you intended to write. If you get a VHDL architecture to compile, it's probably going to approximate to the function you wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has some features that make it good for system-level modeling, whereas Verilog is much better than VHDL at gate-level simulation.

Top 50 Interview Questions

Review these typical interview questions and think about how you would answer them. Read
the questions listed; you will also find some strategy suggestions with it.

1. Tell me about yourself:
The most often asked question in interviews. You need to have a short statement prepared
in your mind. Be careful that it does not sound rehearsed. Limit it to work-related items
unless instructed otherwise. Talk about things you have done and jobs you have held that
relate to the position you are interviewing for. Start with the item farthest back and work up
to the present.

2. Why did you leave your last job?
Stay positive regardless of the circumstances. Never refer to a major problem with
management and never speak ill of supervisors, co-workers or the organization. If you do,
you will be the one looking bad. Keep smiling and talk about leaving for a positive reason
such as an opportunity, a chance to do something special or other forward-looking reasons.

3. What experience do you have in this field?
Speak about specifics that relate to the position you are applying for. If you do not have
specific experience, get as close as you can.

4. Do you consider yourself successful?
You should always answer yes and briefly explain why. A good explanation is that you have
set goals, and you have met some and are on track to achieve the others.

5. What do co-workers say about you?
Be prepared with a quote or two from co-workers. Either a specific statement or a
paraphrase will work. Jill Clark, a co-worker at Smith Company, always said I was the
hardest workers she had ever known. It is as powerful as Jill having said it at the interview
herself.

6. What do you know about this organization?
This question is one reason to do some research on the organization before the interview.
Find out where they have been and where they are going. What are the current issues and
who are the major players?

7. What have you done to improve your knowledge in the last year?
Try to include improvement activities that relate to the job. A wide variety of activities can
be mentioned as positive self-improvement. Have some good ones handy to mention.

8. Are you applying for other jobs?
Be honest but do not spend a lot of time in this area. Keep the focus on this job and what
you can do for this organization. Anything else is a distraction.

9. Why do you want to work for this organization?
This may take some thought and certainly, should be based on the research you have done
on the organization. Sincerity is extremely important here and will easily be sensed. Relate
it to your long-term career goals.

10. Do you know anyone who works for us?
Be aware of the policy on relatives working for the organization. This can affect your answer
even though they asked about friends not relatives. Be careful to mention a friend only if
they are well thought of.

11. What kind of salary do you need?
A loaded question. A nasty little game that you will probably lose if you answer first. So, do
not answer it. Instead, say something like, That's a tough question. Can you tell me the
range for this position? In most cases, the interviewer, taken off guard, will tell you. If not,
say that it can depend on the details of the job. Then give a wide range.

12. Are you a team player?
You are, of course, a team player. Be sure to have examples ready. Specifics that show you
often perform for the good of the team rather than for yourself are good evidence of your
team attitude. Do not brag, just say it in a matter-of-fact tone. This is a key point.

13. How long would you expect to work for us if hired?
Specifics here are not good. Something like this should work: I'd like it to be a long time. Or
As long as we both feel I'm doing a good job.

14. Have you ever had to fire anyone? How did you feel about that?
This is serious. Do not make light of it or in any way seem like you like to fire people. At the
same time, you will do it when it is the right thing to do. When it comes to the organization
versus the individual who has created a harmful situation, you will protect the organization.
Remember firing is not the same as layoff or reduction in force.

15. What is your philosophy towards work?
The interviewer is not looking for a long or flowery dissertation here. Do you have strong
feelings that the job gets done? Yes. That's the type of answer that works best here. Short
and positive, showing a benefit to the organization.

16. If you had enough money to retire right now, would you?
Answer yes if you would. But since you need to work, this is the type of work you prefer. Do
not say yes if you do not mean it.

17. Have you ever been asked to leave a position?
If you have not, say no. If you have, be honest, brief and avoid saying negative things
about the people or organization involved.

18. Explain how you would be an asset to this organization
You should be anxious for this question. It gives you a chance to highlight your best points
as they relate to the position being discussed. Give a little advance thought to this
relationship.

19. Why should we hire you?
Point out how your assets meet what the organization needs. Do not mention any other
candidates to make a comparison.

20. Tell me about a suggestion you have made
Have a good one ready. Be sure and use a suggestion that was accepted and was then
considered successful. One related to the type of work applied for is a real plus.

21. What irritates you about co-workers?
This is a trap question. Think real hard but fail to come up with anything that irritates you.
A short statement that you seem to get along with folks is great.

22. What is your greatest strength?
Numerous answers are good, just stay positive. A few good examples:
Your ability to prioritize, Your problem-solving skills, Your ability to work under pressure,
Your ability to focus on projects, Your professional expertise, Your leadership skills, Your
positive attitude .

23. Tell me about your dream job.
Stay away from a specific job. You cannot win. If you say the job you are contending for is it, you strain credibility. If you say another job is it, you plant the suspicion that you will be dissatisfied with this position if hired. The best is to stay genetic and say something like:
A job where I love the work, like the people, can contribute and can't wait to get to work.

24. Why do you think you would do well at this job?
Give several reasons and include skills, experience and interest.

25. What are you looking for in a job?
See answer # 23

26. What kind of person would you refuse to work with?
Do not be trivial. It would take disloyalty to the organization, violence or lawbreaking to get
you to object. Minor objections will label you as a whiner.

27. What is more important to you: the money or the work?
Money is always important, but the work is the most important. There is no better answer.

28. What would your previous supervisor say your strongest point is?
There are numerous good possibilities:
Loyalty, Energy, Positive attitude, Leadership, Team player, Expertise, Initiative, Patience,
Hard work, Creativity, Problem solver

29. Tell me about a problem you had with a supervisor
Biggest trap of all. This is a test to see if you will speak ill of your boss. If you fall for it and
tell about a problem with a former boss, you may well below the interview right there. Stay
positive and develop a poor memory about any trouble with a supervisor.

30. What has disappointed you about a job?
Don't get trivial or negative. Safe areas are few but can include:
Not enough of a challenge. You were laid off in a reduction Company did not win a contract,
which would have given you more responsibility.

31. Tell me about your ability to work under pressure.
You may say that you thrive under certain types of pressure. Give an example that relates
to the type of position applied for.

32. Do your skills match this job or another job more closely?
Probably this one. Do not give fuel to the suspicion that you may want another job more
than this one.

33. What motivates you to do your best on the job?
This is a personal trait that only you can say, but good examples are:
Challenge, Achievement, Recognition

34. Are you willing to work overtime? Nights? Weekends?
This is up to you. Be totally honest.

35. How would you know you were successful on this job?
Several ways are good measures:
You set high standards for yourself and meet them. Your outcomes are a success.Your boss
tell you that you are successful

36. Would you be willing to relocate if required?
You should be clear on this with your family prior to the interview if you think there is a
chance it may come up. Do not say yes just to get the job if the real answer is no. This can
create a lot of problems later on in your career. Be honest at this point and save yourself
future grief.

37. Are you willing to put the interests of the organization ahead of your own?
This is a straight loyalty and dedication question. Do not worry about the deep ethical and
philosophical implications. Just say yes.

38. Describe your management style.
Try to avoid labels. Some of the more common labels, like progressive, salesman or
consensus, can have several meanings or descriptions depending on which management
expert you listen to. The situational style is safe, because it says you will manage according
to the situation, instead of one size fits all.

39. What have you learned from mistakes on the job?
Here you have to come up with something or you strain credibility. Make it small, well
intentioned mistake with a positive lesson learned. An example would be working too far
ahead of colleagues on a project and thus throwing coordination off.

40. Do you have any blind spots?
Trick question. If you know about blind spots, they are no longer blind spots. Do not reveal
any personal areas of concern here. Let them do their own discovery on your bad points. Do
not hand it to them.

41. If you were hiring a person for this job, what would you look for?
Be careful to mention traits that are needed and that you have.

42. Do you think you are overqualified for this position?
Regardless of your qualifications, state that you are very well qualified for the position.

43. How do you propose to compensate for your lack of experience?
First, if you have experience that the interviewer does not know about, bring that up: Then,
point out (if true) that you are a hard working quick learner.

44. What qualities do you look for in a boss?
Be generic and positive. Safe qualities are knowledgeable, a sense of humor, fair, loyal to
subordinates and holder of high standards. All bosses think they have these traits.

45. Tell me about a time when you helped resolve a dispute between others.
Pick a specific incident. Concentrate on your problem solving technique and not the dispute
you settled.

46. What position do you prefer on a team working on a project?
Be honest. If you are comfortable in different roles, point that out.

47. Describe your work ethic.
Emphasize benefits to the organization. Things like, determination to get the job done and
work hard but enjoy your work are good.

48. What has been your biggest professional disappointment?
Be sure that you refer to something that was beyond your control. Show acceptance and no
negative feelings.

49. Tell me about the most fun you have had on the job.
Talk about having fun by accomplishing something for the organization.

50. Do you have any questions for me?
Always have some questions prepared. Questions prepared where you will be an asset to
the organization are good. How soon will I be able to be productive? and What type of
projects will I be able to assist on? are examples.

VLSI Interview Questions-1

1.What is the difference between mealy and moore state-machines.
2.How to solve setup and hold violations in the design.
3.What is antenna violation & ways to prevent it.
4.We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage.
5.What is tie-high and tie-low cells and where it is used.
6.What is the difference between latches and flip-flops based designs.
7.What is High-Vt and Low Vt cells.
8.What is LEF mean?
9.What is DEF mean?
10.Steps involved in designing an optimal padring.
11.What is metastability and steps to prevent it.
12.What is local-skew, global skew and useful skew.
13.What are the various timing-paths which i should take care in my STA runs?
14.What are the various components of leakage-power.
15.What are the various yield losses in the design.
16.What is meant by virtual clock definition and why do i need it.
17.What are the various variations which impacts timing of the design.
18.What are the various Design constraints used, while performing synthesis for a design.
19.Specify few verilog constructs which are not supported by the synthesis tool.
20.What are the various capacitances with an MOSFET?
21.Vds-Ids curve for an MOSFET, with increasing Vgs.
22.Explain basic operation of an MOSFET.
23.what is channel length modulation.
24.what is body effect.
25.what is latchup in CMOS design and ways to prevent it?
26.what are the various design changes you do to meet design power targets.
27.what is meant by library characterization.
28.what is meant by wireload model.
29.what are the measures to be taken to design for optimized area.
30.what all will you be thinking while performing floorplan.
31.what are the measures in the design taken for meeting signal integrity targets.
32.what are the measures taken in the Design achieving better yield.
33.what are the measures or precautions to be taken in the design when the chip has both analog and digital portions..
34.what are the steps incorporated for Engineering Change order[ECO].
35.what are the steps performed to achieve Lithography friendly Design.
36.what does synthesis mean?
37.what are the pre-requistes to perform synthesis.
38.Can you explain the synthesis flow.
39.what are the various ways to reduce clock insertion delay in the design.
40.what are the various functional verification methodologies.
41.what does formal verification mean.
42.How will you time the output path in STA.
43.How will you time the input path in STA.
44.What is false path mean in STA and in what scenarios falsepath can come.
45.What does multicycle path mean in STA and in what scenarios MCP can come.
46.What are source synchronous paths in STA.
47.Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it..
48.we have multiple instances in RTL, do you do anything special during synthesis stage.
49.What do you call an event and when do you call an assertion.

VLSI Interview Questions-1

1. what is the difference between mealy and moore state-machines
2. how to solve setup and hold violations in the design
3. what is antenna violation & ways to prevent it
4. we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
5. what is tie-high and tie-low cells and where it is used
6. what is the difference between latches and flip-flops based designs
7. what is High-Vt and Low Vt cells
8. what is LEF mean?
9. what is DEF mean?
10. steps involved in designing an optimal padring
11. what is metastability and steps to prevent it
12. what is local-skew, global skew and useful skew
13. what are the various timing-paths which i should take care in my STA runs?
14. what are the various components of leakage-power
15. what are the various yield losses in the design
16. what is meant by virtual clock definition and why do i need it
17. what are the various variations which impacts timing of the design
18. what are the various Design constraints used, while performing synthesis for a design
19. specify few verilog constructs which are not supported by the synthesis tool
20. what are the various capacitances with an MOSFET?
21. Vds-Ids curve for an MOSFET, with increasing Vgs
22. explain basic operation of an MOSFET
23. what is channel length modulation
24. what is body effect
25. what is latchup in CMOS design and ways to prevent it?
26. what are the various design changes you do to meet design power targets
27. what is meant by library characterization
28. what is meant by wireload model
29. what are the measures to be taken to design for optimized area
30. what all will you be thinking while performing floorplan
31. what are the measures in the design taken for meeting signal integrity targets
32. what are the measures taken in the Design achieving better yield
33. what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
34. what are the steps incorporated for Engineering Change order[ECO]
35. what are the steps performed to achieve Lithography friendly Design
36. what does synthesis mean?
37. what are the pre-requistes to perform synthesis
38. can you explain the synthesis flow
39. what are the various ways to reduce clock insertion delay in the design
40. what are the various functional verification methodologies
41. what does formal verification mean
42. how will you time the output path in STA
43. how will you time the input path in STA
44. what is false path mean in STA and in what scenarios falsepath can come
45. what does multicycle path mean in STA and in what scenarios MCP can come
46. what are source synchronous paths in STA
47. Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it.
48. we have multiple instances in RTL, do you do anything special during synthesis stage
49. what do you call an event and when do you call an assertion.
50. what is difference between FPGA and ASIC.

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