Johnson Counter

The Johnson counter, also called the twisted ring counter, is a variation of the ring counter, with the inverse output of the most significant flip-flop passed to the input of the least significant flip-flop. The sequence followed begins with all 0's in the register. The final 0 will cause 1's to be shifted into the register from the left-hand side when clock pulses are applied. When the first 1 reaches the most significant flip-flop, 0's will be inserted into the first flip-flop because of the cross-coupling between the output and the input of the counter.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters
• BCD Counter
• Ring counters

Ring counter

A ring counter is a circular shift register with only one flip-flop being set at any particular time; all others are cleared. The single bit is shifted from one flip-flop to the other to produce the sequence of timing signals.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters
• BCD Counter
• Johnson counters

BCD Counter

A BCD counter counts in binary-coded decimal from 0000 to 1001 and back to 0000. Because of the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight binary count.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters 

• Ring Counter
• Johnson counters

Loadable Counters

Instead of counting from 0, a counter can be made to count from a given initial value. This type of counter is called a loadable counter.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• BCD counters
• Ring counters
• Johnson counters

How are counters made?

Counters are generally made up of flip-flops and logic gates. Like flip-flops, counters can retain an output state after the input condition which brought about that state has been removed. Consequently, digital counters are classified as sequential circuits. While a flip-flop can occupy one of only two possible sattes, a counter can have many more than two states. In the case of a counter, the value of a state is expressed as a multidigit binary number, whose `1's and `0's are usually derived from the outputs of internal flip-flops that make up the counter. The number of states a counter may have is limited only by the amount of electronic hardware that is available. The main types of flip-flops used are J-K flip-flops or T flip-flops, which are J-K flip-flops with both J and K inputs tied together. Before that, here's a quick reminder of how a J-K flip-flop works:

J input	K input	Output, Q
0	0	Q
0	1	0
1	0	1
1	1	not Q

T flip-flops are used because set/reset ([1,0] [0,1]) functions are seldom used. Only the "do nothing" and toggle ([0,0] [1,1]) functions are used. Logic gates are used to decide when to toggle which outputs. Below is an example of a synchronous binary counter, implemented using J-K flip-flops and AND gates.

Read More

• Why do we need counters?

• Synchronous Counter

• Why “Synchronous”?

• Different type of counters

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2-bit Counter VHDL Code

library ieee;
use ieee.std_logic_1164.all;

entity bit_counter is
  port (
    clk       : in  std_logic;
    rst       : in  std_logic;
    count_out : out std_logic_vector(1 downto 0));

end bit_counter;

architecture bit_counter_ar of bit_counter is

-- Defining Internal Signals

signal sig1,sig2 : std_logic;
  signal count_out_sig : std_logic_vector (1 downto 0);

begin  -- 2bit_counter_ar

   process (clk, rst)

-- purpose: sequential part of counter
  -- type   : sequential
  -- inputs : clk, rst
  -- outputs:

  begin  -- process
    if rst = '1' then                   -- asynchronous reset (active high)
      count_out_sig <= "11";
    elsif clk'event and clk = '1' then  -- rising clock edge
      count_out_sig(0) <= sig1;
      count_out_sig(1) <= sig2;
    end if;
  end process;

-- Combinational Logic 

  sig1 <= not count_out_sig(0);
  sig2 <= count_out_sig(1) xor count_out_sig(0);
  count_out <= count_out_sig;

end bit_counter_ar;

Application of Synchronous “up/down” counters

Up/down counter circuits are very useful devices. A common application is in machine motion control, where devices called rotary shaft encoders convert mechanical rotation into a series of electrical pulses, these pulses "clocking" a counter circuit to track total motion:

As the machine moves, it turns the encoder shaft, making and breaking the light beam between LED and phototransistor, thereby generating clock pulses to increment the counter circuit. Thus, the counter integrates, or accumulates, total motion of the shaft, serving as an electronic indication of how far the machine has moved. If all we care about is tracking total motion, and do not care to account for changes in the direction of motion, this arrangement will suffice. However, if we wish the counter to increment with one direction of motion and decrement with the reverse direction of motion, we must use an up/down counter, and an encoder/decoding circuit having the ability to discriminate between different directions.

If we re-design the encoder to have two sets of LED/phototransistor pairs, those pairs aligned such that their square-wave output signals are 90^o out of phase with each other, we have what is known as a quadrature output encoder (the word "quadrature" simply refers to a 90^o angular separation). A phase detection circuit may be made from a D-type flip-flop, to distinguish a clockwise pulse sequence from a counter-clockwise pulse sequence:

When the encoder rotates clockwise, the "D" input signal square-wave will lead the "C" input square-wave, meaning that the "D" input will already be "high" when the "C" transitions from "low" to "high," thus setting the D-type flip-flop (making the Q output "high") with every clock pulse. A "high" Q output places the counter into the "Up" count mode, and any clock pulses received by the clock from the encoder (from either LED) will increment it. Conversely, when the encoder reverses rotation, the "D" input will lag behind the "C" input waveform, meaning that it will be "low" when the "C" waveform transitions from "low" to "high," forcing the D-type flip-flop into the reset state (making the Q output "low") with every clock pulse. This "low" signal commands the counter circuit to decrement with every clock pulse from the encoder.

This circuit, or something very much like it, is at the heart of every position-measuring circuit based on a pulse encoder sensor. Such applications are very common in robotics, CNC machine tool control, and other applications involving the measurement of reversible, mechanical motion.

• Synchronous counters
• Different type of synchronous counters
• Synchronous “up” counter
• Synchronous “down counter
• Synchronous “up/down”counter

4-bit Synchronous “down” counter

To make a synchronous "down" counter, we need to build the circuit to recognize the appropriate bit patterns predicting each toggle state while counting down. Not surprisingly, when we examine the four-bit binary count sequence, we see that all preceding bits are "low" prior to a toggle (following the sequence from bottom to top):

Since each J-K flip-flop comes equipped with a Q' output as well as a Q output, we can use the Q' outputs to enable the toggle mode on each succeeding flip-flop, being that each Q' will be "high" every time that the respective Q is "low:"

Links :

• Synchronous counters
• Different type of synchronous counters
• Synchronous “up” counter
• Synchronous “up/down”counter
• Application of “up/down” counter

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4-bit Synchronous “up” Counter

Examining the four-bit binary count sequence, another predictive pattern can be seen. Notice that just before a bit toggles, all preceding bits are "high:"

This pattern is also something we can exploit in designing a counter circuit. If we enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are "high," we can obtain the same counting sequence as the asynchronous circuit without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time:

The result is a four-bit synchronous "up" counter. Each of the higher-order flip-flops are made ready to toggle (both J and K inputs "high") if the Q outputs of all previous flip-flops are "high." Otherwise, the J and K inputs for that flip-flop will both be "low," placing it into the "latch" mode where it will maintain its present output state at the next clock pulse. Since the first (LSB) flip-flop needs to toggle at every clock pulse, its J and K inputs are connected to V_cc or V_dd, where they will be "high" all the time. The next flip-flop need only "recognize" that the first flip-flop's Q output is high to be made ready to toggle, so no AND gate is needed. However, the remaining flip-flops should be made ready to toggle only when all lower-order output bits are "high," thus the need for AND gates.

Links :

• Synchronous counters
• Different type of synchronous counters
• Synchronous “down” counter
• Synchronous “up/down” counter
• Application of “up/down” counter

Synchronous “up/down” Counter

We can build a counter circuit with selectable between "up" and "down" count modes by having dual lines of AND gates detecting the appropriate bit conditions for an "up" and a "down" counting sequence, respectively, then use OR gates to combine the AND gate outputs to the J and K inputs of each succeeding flip-flop:

This circuit isn't as complex as it might first appear. The Up/Down control input line simply enables either the upper string or lower string of AND gates to pass the Q/Q' outputs to the succeeding stages of flip-flops. If the Up/Down control line is "high," the top AND gates become enabled, and the circuit functions exactly the same as the first ("up") synchronous counter circuit shown in this section. If the Up/Down control line is made "low," the bottom AND gates become enabled, and the circuit functions identically to the second ("down" counter) circuit shown in this section.

To illustrate, here is a diagram showing the circuit in the "up" counting mode (all disabled circuitry shown in grey rather than black):

 

Here, shown in the "down" counting mode, with the same grey coloring representing disabled circuitry:

Links:

• Synchronous Counters
• Different type of counters
• Synchronous “up” counter
• Synchronous “down” counter
• Application of “up/down” counter

Different type of synchronous counters

A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time.

In electronics, synchronous counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:

• Binary counters
• Up/down counters
• Loadable counters
• BCD counters
• Ring counters
• Johnson counters

Binary counters

Binary counters are the simplest form of counters. An N-bit binary counter counts from 0 to (2^N - 1) and back to 0 again.

 

Links:

Different types of counters

Up/down counters

Loadable counters

BCD counters

Ring counters

Johnson counters

Why “synchronous”?

• The difference between asynchronous and synchronous counters.

In an asynchronous counter, an external event is used to directly SET or CLEAR a flip-flop when it occurs. In a synchronous counter however, the external event is used to produce a pulse that is synchronised with the internal clock. An example of an asynchronous counter is a ripple counter. Each flip-flop in the ripple counter is clocked by the output from the previous flip-flop. Only the first flip-flop is clocked by an external clock. Below is an example of a 4-bit ripple counter.

• Dangers of asynchronous counters.

Although the asynchronous counter is easier to implement, it is more "dangerous" than the synchronous counter. In a complex system, there are many state changes on each clock edge, and some IC's (integrated circuits) respond faster than others. If an external event is allowed to affect a system whenever it occurs, a small percentage of the time it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. What is worse, these problems are difficult to test for and difficult to foresee because of the random time difference between the events.

 

Links:

• Why do we need counters?
• How are counters made?
• Synchronous Counter.
• Different type of counters

Why do we need counters ?

In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting.

A timing problem might require that a high-frequency pulse train, such as the output of a 10-MHz crystal oscillator, be divided to produce a pulse train of a much lower frequency, say 1 Hz. This application is required in a precision digital clock, where it is not possible to build a crystal oscillator whose natural frequency is 1 Hz.

A sequencing problem would arise if, for instance, it became necessary to apply power to various components of a large machine in a specific order. The starting of a rocket motor is an example where the energizing of fuel pumps, ignition, and possibly explosive bolts for staging must follow a critical order.

Measuring the flow of auto traffic on roadway is an application in which an event (the passage of a vehicle) must increment a tally. This can be done automatically with an electronic counter triggered by a photocell or road sensor. In this way, the total number of vehicles passing a certain point can be counted.

Links:

• How are counters made?
• Why “Synchronous”?
• Synchronous Counter
• Different type of counters

Synchronous Counter

The purpose of writing this is to collate information on Digital Synchronous Counters. Particular emphasis was placed on the following areas :

1. Types of Synchronous Counters and How they work

2. Fast Counter Techniques

3. Implementation of Counters :

4. Dedicated Hardware and Alternative Devices

According to the Oxford Encyclopædic Dictionary:

synchronous adj. existing or occurring at the same time.

counter n. an apparatus used for counting. || a person or thing that counts.

So a "synchronous counter" should mean "a person, thing or apparatus that counts at the same time" ?!?! Hmmm...

Let us take a look at the definition given by the IBM Dictionary of Computing instead.

synchronous (1) Pertaining to two or more processes that depend upon the occurrence of specific events such as common timing signals. (2) Occurring with a regular or predictable time relationship.

counter (1) A functional unit with a finite number of states each of which represents a number that can be, upon receipt of an appropriate signal, increased by unity or by a given constant. This device is usually capable of bringing the represented number to a specified value; for example zero.

So a "synchronous counter" is actually a functional unit with a certain number of states, each representing a number which can be increaced or decreased upon receiving an appropriate signal (e.g. a rising edge pulse), and is usually used to count to, or count down to zero from, a specified number N.

... and what it "really" means. OK! Enough of dictionary definitions.

Basically, any sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses, called count pulses, may be clock pulses or they may originate from an external source and may occur at prescribed intervals of time or at random. The sequence of states in a counter may follow a binary count or any other sequence.

 

Read More

• Why do we need counters?
• How are counters made?
• Why “Synchronous”?
• Different type of counters