64 core processor from Chinese chip maker Phytium

While the world awaits the AMD K12 and Qualcomm Hydra ARM server chips to join the ranks of the Applied Micro X-Gene and Cavium ThunderX processors already in the market, it could be upstart Chinese chip maker Phytium Technology that gets a brawny chip into the field first and also gets traction among actual datacenter server customers, not just tire kickers.

Phytium Technology has announced a 64-core ARM server CPU, which according to the press release will deliver 512 gigaflops of performance. The new chip, known as FT-2000/64, is aimed at “high throughput and high performance servers.”

Phytium is a chip design enterprise, based in Tianjin, China. In March 2015, the company released its first products: the FT-1500A/4 and FT-1500A/16, 4-core and 16-core implementations, respectively of the ARMv8 design.

Phytium was on hand at last week’s Hot Chips 28 conference, showing off its chippery and laptop, desktop and server machines employing its “Earth” and “Mars” FT series of ARM chips. Most of the interest that people showed in the server variants, which are both based on variants of the “Xiaomi” core design that the company has cooked up based on ARMv8 intellectual property licensed from ARM Holdings. There is chatter that one of the three Chinese exascale machines, which we wrote about here, will employ a future Phytium processor, but we were unable to confirm this with the Phytium executives at the event. What we can tell you is that the first engineering samples of the two Earth ARM chips, the FT-1500A/4 and the FT-1500A/16, as well as the one Mars ARM chip, the FT-2000/64, are back from Taiwan Semiconductor Manufacturing Corp and that we saw systems running the Kylin Linux operating system (a variant of Canonical’s Ubuntu) at the Hot Chips event.

Here are the key chip features from the FT-2000/64 product page: 

• Process：Manufacturing with 28nm process
• Core：Integrating sixty-four FTC661 cores
• Frequency：Running at 1.5GHz~2.0GHz
• Cache：Integrating 32MB L2 cache and extending 128MB LLC
• Extension Interface：Integrating eight proprietary extension interfaces, each delivering 19.2GB/s effective r/w bandwidth
• Memory Interface：Extending sixteen DDR3-1600 memory controllers, which can deliver 204.8GB/s memory access bandwidth.
• I/O Interface：Integrating two x16 or four x8 PCIE Gen3 interface
• Power：Max. power 100W
• Package：FCBGA package with 2892 pins

No pricing was provided on the new chips, and it’s unclear from the press release if the product is available today. The next time we hear about the FT-2000/64 might very well be when it shows up in a TOP500 supercomputer. Stay tuned.

The World's First 1,000 Processor Chip ( KiloCore Chip )

A team of scientists from the University of California has created the world's first microchip with 1,000 independent processors. Called 'KiloCore' chip, it is also claimed to be the world's fastest chip ever designed at a university. The chip, which was presented this week at the 2016 Symposium on VLSI Technology and Circuits, is capable of 1.78 trillion instructions per second and contains 621 million transistors. The partially Department of Defense-funded KiloCore chip was ultimately built by IBM using existing 32 nanometer semiconductor fabrication technology.

Unfortunately, a 1,000 core chip isn't something that could just be plugged into the next line of MacBook Pros. It wouldn't even really suffice as a graphics processor, where massively parallel computation is the norm. In fact, many GPUs exceed the 1,000 cores of the UC Davis chip, but with the caveat that the individual cores are directed according to a central controller. The KiloCore, by contrast, is built from completely independent cores capable of running completely independent computer programs.

Here's all you need to know about the chip:

• This microchip has been designed by a team at the University of California, Davis, Department of Electrical and Computer Engineering.
• KiloCore chip executes instructions more than 100 times more efficiently than a modern laptop processor.
• Each processor core can run its own small program independently of the others, which is a fundamentally more flexible approach than the Single-Instruction-Multiple-Data approaches utilized by processors such as graphics processing unit (GPU). Because each processor is independently clocked, it can shut itself down to further save energy when not needed.
• The chip has been fabricated by IBM using its 32nm CMOS technology. KiloCore's each processor core can run its own small program independently of the others.
• Cores operate at an average maximum clock frequency of 1.78 GHz, and they transfer data directly to each other rather than using a pooled memory area that can become a bottleneck for data.

The independence of the cores makes the KiloCore chip a multiple instruction multiple data (MIMD) computer. This is in contrast to the more typical single instruction multiple data (SIMD) variety of parallel computation, as would be expected in a graphics processor. A SIMD machine's version of parallelism is to implement the same single operation across many different cores - that is, do the same thing to many different units of data. This is the norm in image processing, for example, where a lot of different pixels holding different a lot of different values are all updated in the same way. A MIMD machine can be expected to do much more complex calculations.

Together, the 1,000 processors can execute 115 billion instructions per second while dissipating only 0.7 Watts. As noted in a UC Davis press release, this power requirement is low enough that it could be supplied by a single AA battery, achieving an efficiency of around 100 times that of a normal laptop processor.

The energy savings here largely has to do with the abandoning of the traditional system memory architecture, in which data for multiple cores is stored in a central RAM unit. Rather than sharing data in this way, the KiloCore chip uses a built-in networking scheme in which data is transferred directly between the different processors using packet- and circuit-switched networking.