4μm thick fabric like flexible circuit

According to the Korea Advanced Institute of Science and Technology (KAIST), complete with substrate, an active matrix for a flexible display need only be 4μm thick. 

Initially on a sacrificial laser-reactive substrate the matrix of ultra-thin n-type transparent oxide thin-film transistors (TFTs) were fabricated for the back plane.

Laser irradiation from the backside of the substrate split off only the oxide TFT array as a result of reaction with the laser-reactive layer.

The free transistors were transferred to a 4μm  polyethylene terephthalate (PET) substrate, and then the combination was further transferred con-formally to the surface of human skin and artificial leather to demonstrate the possibility of the wearable application.

“The attached oxide TFTs showed high optical transparency of 83% and 40cm2/Vs even under several cycles of severe bending tests,” said KAIST.

The method is called inorganic-based laser lift-off (ILLO).

“By using our ILLO process, the technological barriers for high performance transparent flexible displays have been overcome at a relatively low cost by removing expensive polyimide substrates. Moreover, the high-quality oxide semiconductor can be easily transferred onto skin-like, or any flexible, substrate for wearable application,” said Professor Keon Jae Lee.

Con-formal displays are a potential application.

“With the advent of the Internet of Things era, demand has grown for wearable and transparent displays that can be applied to fields such as augmented reality and skin-like thin flexible devices,” said KAIST. “However, previous flexible transparent displays have poor transparency and low electrical performance. To improve the transparency and performance, past research efforts have tried to use inorganic-based electronics, but the fundamental thermal instabilities of plastic substrates have hampered the high temperature process, an essential step necessary for the fabrication of high performance electronic devices.”

The World's First 1,000 Processor Chip ( KiloCore Chip )

A team of scientists from the University of California has created the world's first microchip with 1,000 independent processors. Called 'KiloCore' chip, it is also claimed to be the world's fastest chip ever designed at a university. The chip, which was presented this week at the 2016 Symposium on VLSI Technology and Circuits, is capable of 1.78 trillion instructions per second and contains 621 million transistors. The partially Department of Defense-funded KiloCore chip was ultimately built by IBM using existing 32 nanometer semiconductor fabrication technology.

Unfortunately, a 1,000 core chip isn't something that could just be plugged into the next line of MacBook Pros. It wouldn't even really suffice as a graphics processor, where massively parallel computation is the norm. In fact, many GPUs exceed the 1,000 cores of the UC Davis chip, but with the caveat that the individual cores are directed according to a central controller. The KiloCore, by contrast, is built from completely independent cores capable of running completely independent computer programs.

Here's all you need to know about the chip:

• This microchip has been designed by a team at the University of California, Davis, Department of Electrical and Computer Engineering.
• KiloCore chip executes instructions more than 100 times more efficiently than a modern laptop processor.
• Each processor core can run its own small program independently of the others, which is a fundamentally more flexible approach than the Single-Instruction-Multiple-Data approaches utilized by processors such as graphics processing unit (GPU). Because each processor is independently clocked, it can shut itself down to further save energy when not needed.
• The chip has been fabricated by IBM using its 32nm CMOS technology. KiloCore's each processor core can run its own small program independently of the others.
• Cores operate at an average maximum clock frequency of 1.78 GHz, and they transfer data directly to each other rather than using a pooled memory area that can become a bottleneck for data.

The independence of the cores makes the KiloCore chip a multiple instruction multiple data (MIMD) computer. This is in contrast to the more typical single instruction multiple data (SIMD) variety of parallel computation, as would be expected in a graphics processor. A SIMD machine's version of parallelism is to implement the same single operation across many different cores - that is, do the same thing to many different units of data. This is the norm in image processing, for example, where a lot of different pixels holding different a lot of different values are all updated in the same way. A MIMD machine can be expected to do much more complex calculations.

Together, the 1,000 processors can execute 115 billion instructions per second while dissipating only 0.7 Watts. As noted in a UC Davis press release, this power requirement is low enough that it could be supplied by a single AA battery, achieving an efficiency of around 100 times that of a normal laptop processor.

The energy savings here largely has to do with the abandoning of the traditional system memory architecture, in which data for multiple cores is stored in a central RAM unit. Rather than sharing data in this way, the KiloCore chip uses a built-in networking scheme in which data is transferred directly between the different processors using packet- and circuit-switched networking.

IBM steps forward to replace Silicon Transistors with Carbon Nanotubes

Carbon Nanotube

The breakthrough is that - IBM improves carbon nanotube scaling below 10nm. How ever before calling it as breakthrough we should also check out what other giants like Intel, AMD, TSMC or Samsung is working on. This breakthrough has relation with the Moore's Law. Yes you got right..!!It says that the transistor counts double only every 18 month or so. It’s the time that Intel marks 40 years of the 4004 microprocessor and here now lying some fear that progress will soon hit a wall.

You can refer to my post History and Evolution of Integrated Circuits where it shows clear progress of semiconductor industry.

But not to worry, IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips to support Moore's law. These chips will be both faster and more power efficient.

Few glimpse of carbon nanotube transistors

• Carbon nanotube transistors can operate at ten nanometers
• Equivalent to 10,000 times thinner than a strand of human hair
• Less than half the size of today’s leading silicon technology
• Could also mean wearables that attach directly to skin and internal organs

Here I have an animation for Animated Nanofactory in Action.

As a result of this the devices will become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now.

These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away.

A project at IBM is now aiming to have transistors built using carbon nanotubes ready to take over from silicon transistors soon after 2020. According to the semiconductor industry’s roadmap, transistors at that point must have features as small as five nanometers to keep up with the continuous miniaturization of computer chips.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology.

IBM's new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry.

By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

IBM’s chosen design uses six nanotubes lined up in parallel to make a single transistor. Each nanotube is 1.4 nanometers wide, about 30 nanometers long, and spaced roughly eight nanometers apart from its neighbors. Both ends of the six tubes are embedded into electrodes that supply current, leaving around 10 nanometers of their lengths exposed in the middle. A third electrode runs perpendicularly underneath this portion of the tubes and switches the transistor on and off to represent digital 1s and 0s.

The IBM team has tested nanotube transistors with that design, but so far it hasn't found a way to position the nanotubes closely enough together, because existing chip technology can’t work at that scale. The favored solution is to chemically label the substrate and nanotubes with compounds that would cause them to self-assemble into position. Those compounds could then be stripped away, leaving the nanotubes arranged correctly and ready to have electrodes and other circuitry added to finish a chip.

Intel's Skylarke Processors for PCs, Tablets and Servers

Intel is launching a full portfolio of "Skylake" processors that company officials expect will combine with Microsoft's Windows 10 operating system to help jump start a stagnant global PC market.

Executives with the chip maker for more than a year have been talking about the 14-nanometer Skylake architecture and the advanced features that are contained within it, touching on everything from graphics and imaging to security, memory, performance and wireless connectivity. In early August, Intel rolled out two Skylake chips—the Core i7-6700K and i5-6600K desktop processors—for gaming machines, and later in the month officials gave out a few more details during the Intel Developer Forum (IDF).

While Intel Corp. is going to release its code-named “Skylake” processors a little later than expected, the company keeps the plan to introduce its new micro-architecture for virtually all segments of the market continuum this year. Intel will roll-out “Skylake” central processing units for tablets, 2-in-1s, personal computers and servers this year, the chip giant confirmed this week.

“When I look at the range of what Skylake’s able to deliver from the Core M level all up to the i7 and Xeon, it’s just going to be a fantastic product,” said Intel CEO Brian Krzanich, in an interview with the IDG News Service at Mobile World Congress in Barcelona.

Intel ran into problems with production of its code-named “Broadwell” processors using 14nm manufacturing technology last year. Due to insufficient yields, the world’s largest maker of microprocessors had to delay introduction of its latest chips by about a year. However, since “Skylake” brings a lot of innovations, Intel did not want to delay it significantly. As a result, “Broadwell” products will have a relatively short lifecycle.

Intel will introduce the first “Skylake” processors in the form of dual-core Core M chips in the third quarter of this calendar year. The CPUs will power high-performance tablets, hybrid 2-in-1 personal computers and ultra-thin notebooks. It is expected that many mobile devices powered by Intel Core M “Skylake” will support Rezence wireless charging and WiGig short-range transmission technology.

In late Q3 or early Q4 the Santa Clara, California-based chip designer will introduce its first Core i3, Core i5 and Core i7 chips featuring “Skylake” micro-architecture for mainstream personal computers, including desktops and laptops. The lineup is projected to include chips with unlocked multiplier designed for enthusiast-class desktop PCs. Systems featuring the new “Skylake” processors will have improved storage performance thanks to native support of SATA Express. In addition, many “Skylake”-powered PCs will use DDR4 memory and support a variety of other innovations.

Intel also plans to introduce Xeon processors with “Skylake” cores for uniprocessor servers later this year. While there are plans to bring “Skylake” architecture to Xeon chips for dual-processor and multi-processor servers, Intel yet has to outline exact plans concerning the move.

Intel “Skylake” processors will be made using 14nm process technology and will feature a brand new micro-architecture that is designed to improve performance and power efficiency of central processing units. Unfortunately, not all “Skylake” processors will support 512-bit AVX 3.2 instructions, according to unofficial information.

Resistive Memory - ReRam

The memory tech that will eventually replace NAND flash, finally in market

What is ReRam?

ReRam is Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material often referred to as a memristor. The biggest advantage of ReRAM technology is its good compatibility with CMOS technologies.

It is under development by a number of companies, and some have already patented their own versions of the technology. The memory operates by changing the resistance of special dielectric material called a memresistor (memory resistor) whose resistance varies depending on the applied voltage.

What makes ReRam?

From the viewpoint of the material choice, the advantage of ReRAM is evident. It is possible to fabricate MOM structures easily by using the oxides widely used in the current semiconductor technologies. Low-current ReRAM operation was reported in the CuOx-based MOM structure. The CuOx layer was grown by the thermal oxidation of the 0.18-μm Cu. NiO and CoO are being intensively studied as oxide materials for ReRAM, and these transition metal elements are also used in metal silicides employed as gate materials. Recently, the good scaling feasibility of ReRAM was demonstrated in an HfOx-based memory with a cell size of 30 nm. The devices in a 1-kbit array exhibited a high device yield (~100%) and robust cycling endurance (>106) with a pulse width of 40 ns. The memory cell consisted of a TiN/Ti/HfOx/TiN structure. Here, the Ti overlayer played the role of oxygen gettering for better ReRAM operation. The gettering effect has already been investigated in HfOx as a high-k material for the gate dielectric films in CMOS devices. The academic and technological knowledge about high-k materials will be very useful in the design of the stacking structure for a ReRAM device.

How ReRam Works?

RRAM is the result of a new kind of dielectric material which is not permanently damaged and fails when dielectric breakdown occurs; for a memresistor, the dielectric breakdown is temporary and reversible. When voltage is deliberately applied to a memresistor, microscopic conductive paths called filaments are created in the material. The filaments are caused by phenomena like metal migration or even physical defects. Filaments can be broken and reversed by applying different external voltages. It is this creation and destruction of filaments in large quantities that allows for storage of digital data. Materials that have memresistor characteristics include oxides of titanium and nickel, some electrolytes, semiconductor materials, and even a few organic compounds have been tested to have these characteristics.

The principal advantage of RRAM over other non-volatile technology is high switching speed. Because of the thinness of the memresistors, it has a great potential for high storage density, greater read and write speeds, lower power usage, and cheaper cost than flash memory. Flash memory cannot continue to scale because of the limits of the materials, so RRAM will soon replace flash memory.

How 450mm wafers will change the semiconductor industry

The semiconductor industry's transition to making chips on 450-millimeter wafers is better described as a "transformation," Jonathan Davis of Semiconductor Equipment and Materials International writes. "The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia," he writes, adding, "However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational."

Even for the segments that continue manufacturing semiconductor devices on 300mm and 200mm silicon wafers, the industry will change dramatically with the introduction of 450mm wafer processing. The 450mm era will impact industry composition, supply chain dynamics, capital spending concentration, future R&D capabilities and many other facets of today’s semiconductor manufacturing industry — not the least of which are the fabs, wafers and tools with which chips are made.

The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia.   For those reasons, the evolutionary tone of “transition” seems appropriate. However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational.

No transformation occurs in isolation and other factors will contribute to the revolutionary qualities of 450mm.  Market factors, new facilities design, next generation processing technology, the changing dynamics of node development and new materials integration will simultaneously affect the industry landscape.

While reading about the implications of 450mm is valuable, I believe that there is much to learn by being a part of the discussion. How is this future transformation being envisioned and acted on today?  I hope that you will join us — at our “live” event, where you will have the opportunity to hear first-hand information… direct from well-informed experts in the industry.

Potential revisions in the 450mm wafer specification are under consideration.  At least two issues are currently being evaluated by the industry and both portend significant ramifications for wafer suppliers, equipment makers and those technologies that interface with the wafer.

First, the wafer orientation method may be revised to eliminate the orientation “notch” on the perimeter of the substrate. The notch was introduced in the 300mm transition as an alternative to the flat.  However, both equipment suppliers and IC makers, through a constructive and collaborative dialog, have concluded that eliminating the notch can potentially improve the die yield, tool performance and cost.

Secondly, reduction of the wafer edge exclusion area — that peripheral portion of the silicon on which no viable device structure occurs — also offers potential yield advantages.  The current 450mm wafer specification (SEMI E76-0710), originally published in 2010, calls for a 2mm edge exclusion zone.  IC makers believe that reduction of this area to a 1.5mm dimension offers the cost equivalence of a 1 percent yield increase.  Though a percent may sound trivial, it is represents substantial increased value over time.

Along with cost and efficiency improvements, IC makers and consortia driving the transition to 450mm manufacturing expect to achieve similar or better environmental performance. Larger footprints and resource demands from 450mm facilities in conjunction with mandates for environmentally aware operations are compelling fabs and suppliers to consider sustainability and systems integration at greater levels than ever before.

Experts in fab facilities, energy, water and equipment engineering will discuss the implications of 450mm to environment, health and safety during the SEMICON West 450mm Manufacturing EHS Forum on Wednesday, July 10.

Included in the presentations are perspectives from the Facility 450 Consortium (F450C) including Ovivo, Edwards and M+W Group.  A holistic Site Resource Model that provides semiconductor manufacturers visibility into effective reduction of total energy and water demands for individual systems, as well as for the entire facility will be reviewed by CH2M Hill. The model is an integrated analytical approach to assess and optimize a semiconductor facility’s thermal energy, electrical energy, and water demand, as well as the cost associated with these resources.

3D IC market to see stable growth through 2016

The global 3D integrated circuit market is forecast to grow by 19.7 percent between 2012 and 2016, with the major growth driver being strong demand for memory products, particularly flash memory and DRAM.

3D integrated circuits help improve the performance and reliability of memory chips, and as an added benefit the resulting chips are smaller and cheaper. However, chips based on 3D circuits face thermal conductivity problems which might pose a challenge to further growth.

According to Infiniti Research, the biggest 3D IC vendors at the moment are Advanced Semiconductor Engineering (ASE), Samsung., STMicroelectronics and Taiwan Semiconductor Manufacturing Co. (TSMC). IBM, Elpida, Intel and Micron are also working on products based on 3D ICs.

Intel was a 3D IC pioneer and it demoed a 3D version of the Pentium 4 back in 2004. The overly complicated chip offered slight performance and efficiency improvements over the 2D version of the chip, which really isn't saying much since Prescott-based Pentium 4s were rubbish.

The focus then shifted on memory chips and some academic implementations of 3D processors, but progress has been relatively slow, hence any growth is more than welcome.

New superfast RFIC developed by Korean Researchers

South Korea has developed a new radio frequency (RF) chip, which it has dubbed the world's fastest wireless technology, capable of sending and receiving 10 gigabits per second over the 60 Gigahertz (Ghz) waveband.

The new RF chip could be a new competitive differentiator for smartphones.

The RF chip was developed by a team from the Korea Advanced Institute of Science and Technology (KAIST), according to a report Tuesday by Yonhap.
For example, the chip can transmit a 4.7 gigabyte movie file in just 3.76 seconds, while the same file transfer would take more than 3 minutes over Wi-Fi and over 200 minutes via Bluetooth.

"It is a key new technology that can greatly increase the competitiveness of the country's smartphones. The chip can also replace various cables that existing televisions require, which means it can be used not only in smartphones but also in other mobile devices, such as cameras," said Park Cheol-soon, a KAIST professor in charge of the research, in the report.
The size of the chip has also been minimized for use in small mobile devices by needing only one antenna for transmission of both outgoing and incoming data, unlike conventional RF chips, noted the report.