VHDL Coding Tips For Excellent Design

Here are the Ten Commandments of Excellent Design:

1. All state machine outputs shall always be registered
2. Thou shalt use registers, never latches
3. Thy state machine inputs, including resets, shall be synchronous
4. Beware fast paths lest they bite thine ankles
5. Minimize skew of thine clocks
6. Cross clock domains with the greatest of caution. Synchronize thy sig- nals!
7. Have no dead states in thy state machines
8. Have no logic with unbroken asynchronous feedback lest the fleas of myriad Test Engineers infest thee
9. All decode logic must be crafted carefully—eschew asynchronicity
10. Trust not thy simulator—it may beguile thee when thy design is junk

How to Write Ten-Commandment Code

Conforming to the Ten Commandments is not difficult. In this section you’ll see how to write VHDL (your author doesn’t do Verilog, but the translation is easy) that complies with the rules. Robust design and first-silicon success are the goals!

The philosophy behind Ten-Commandment code is that synthesizers are not to be trusted too much. Most of the code you will see is close to the structural level; some more overtly than others. Most of the code is self-explanatory. It is assumed that the reader is familiar with VHDL. Signal names are also obvious to anyone “skilled in the art.”

How to Create a Flip-Flop

One of the basic primitives that we need to create robust synchronous designs is the D-type flip-flop. Look at the code in Code Sample 1: A D-type Flip Flop

-- VHDL Code for a D-Type Flip-Flop with an -- Asynchronous Clear

D_Type_Flip_Flop: process(Reset_n, Clock_In)

  begin

    if (Reset_n = ’0’) then

      Q_Output <= ’0’ after 1 ns;

  elsif (Clock_In’event and Clock_In = ’1’) then

      Q_Output <= D_Input after 1 ns;

  end if;

end process D_Type_Flip_Flop;

This flip-flop has the following properties:

• An asynchronous active-low clear input sets the Q output to zero.
• It is triggered on the rising edge of the clock.

How to Create a Latch

While the Ten Commandments specifically forbid the use of latches, there are still those heretics who will insist on the use of latches. The code to instantiate a transparent latch is shown in Code Sample 2: A Transparent Latch

-- VHDL Code for a Transparent Latch

Latch_Data: process(Latch_Open, D_Input)

  begin

    if (Latch_Open = ’1’) then

      Latched_Data <= D_Input;

    -- If Latch_Open = 0, then Latched_Data keeps its old value, -- i.e. the latch is closed.

    end if;

end process Latch_Data;

This latch has the following properties:

• A latch control that opens the latch when high (the latch is transparent).

How to Create a Metastable- Hardened Flip-Flop

The use of a metastable-hardened flip flop is nothing more than the direct instantiation of a suitable library element in this case, a “dfntns” flip-flop. This is pure structural VHDL. The component declaration is shown in Code Sample 3:  A Metastable-Hardened Flip-Flop, Component Declaration

-- VHDL Code for a Nice Metastable-Hardened Flip-Flop

component dfntns

  Port (

    CP : In std_logic;

    D : In std_logic;

    Q : Out std_logic

  );

end component;

To use the flip-flop in your circuit, instantiate it as shown in Code Sample 4: A Metastable-Hardened Flip-Flop, Instantiation

-- VHDL Code to Instantiate the Metastable-Hardened Flip-Flop

Metastable_Hardened_Flip_Flop_Please: dfntns port map (

  D => D_Input,

  CP => Clock_In,

  Q => Q_Output

  );

This flip-flop has the following properties:

• A maximum clock-to-out time under worst-case setup and hold time violations. This time is available in the library element specifications.

The Care and Feeding of Toggle Signals

Receiving a Toggle Signal

The Ten Commandments paper suggested that a method for exchanging single- point information across clock domains is by the use of toggle signals. Here, it is assumed that the toggle event should generate an active-high pulse to pass to a state machine. Every toggle—rising edge and falling edge—must create the pulse. In addition, the pulse must be synchronized correctly to the receiver’s clock. The code to accomplish this is shown in Code Sample 5: Receiving a Toggle Signal

-- VHDL Code to Create a Pulse from an Asynchronous -- Toggle Signal

-- First, use a metastable-hardened flip-flop to synchronize the -- toggle input

Metastable_Hardened_Flip_Flop_Please: dfntns port map (

  D => Handshake_T,

  CP => Clock_In,

  Q => Sync_Handshake_T

  );

-- Now pass the synchronized toggle through another flip-flop

Toggle_Reg_Proc: process(Clock_In)

  begin

    if (Clock_In'event and Clock_In = ’1’) then

      Reg_Handshake_T <= Sync_Handshake_T after 1 ns;

    end if;

  end process Toggle_Reg_Proc;

-- Finally XOR the two synchronized signals to create a pulse

Toggle_Pulse <= Reg_Handshake_T xor Sync_Handshake_T;

When synthesizing this code, remember to use the “fix hold” option so a fast path doesn't occur between the two flip-flops in this circuit.

Generating a Toggle Signal

Recall that a toggle signal is generated by simply inverting a level to pass the information. The trivial code to do this is shown in Code Sample 6:  Generating a Toggle Signal

The suffix “_T” is used to denote a toggle signal.

-- VHDL Code to Create a Toggle Signal

Handshake_T <= not (Handshake_T) after 1 ns;

Coding State Machines
The creation of state machines is a mixture of art and science. A well-crafted state machine will possess a sense of elegance; it will be appealing, both functionally and visually.
Here, a very simple example is presented as an illustration of state machine design. The state diagram for the Flintstones State Machine is shown in figure below popularly known as The Flintstones State Machine.

The Flintstones State Machine operates as follows:

1. The State Machine has two states, State Bed and State Rock.
2. There is one output, Fred, which takes the value 0 in State Bed and 1 in State Rock.
3. A reset, caused by a low level on Reset_n, puts the State Machine into State Bed.
4. The State Machine waits in State Bed while Barney is low, and enters State Rock when Barney goes high.
5. The State Machine then waits in State Rock while Wilma is low, and returns to State Bed when Wilma goes high.

Implementing the Flintstones State Machine

An example implementation of the Flintstones State Machine is shown in Code Sample 7 below:

-- VHDL Code to Implement the Flintstones State Machine

Flintstones_SM_Proc: process(Sync_Reset_n, Clock_In)

  -- Enumerate state types:

  type Flintstones_Statetype is (

  Bed, Rock

  );

  -- define the state variable:

  variable Flint_State: Flintstones_Statetype;

  -- Here’s the state machine:

  begin

  -- Define the asynchronously set reset states...

    if (Sync_Reset_n = ’0’) then

      Fred <= ’0’ after 1 ns;

      Flint_State := Bed

      -- Default conditions for each output, in this case identical to the -- reset state:

    elsif (Clock_In’event and Clock_In = ’1’) then

      Fred <= ’0’ after 1 ns;

    -- Here are the state transitions:

    case Flint_State is

      when Bed =>

      -- Transition from Bed to Rock:

        if (Barney = ’1’) then

          Fred <= ’1’ after 1 ns;

          Flint_State := Rock;

          -- Holding term in Bed:

        else

          Flint_State := Bed;

        end if;

      when Rock =>

        -- Transition from Rock to Bed:

        if (Wilma = ’1’) then

          Fred <= ’0’ after 1 ns;

          Flint_State := Bed;

        -- Holding term in Rock:

        else

          Fred <= ’1’ after 1 ns;

          Flint_State := Rock;

        end if;

      -- Default term for dead states:

      when others =>

        Flint_State := Bed;

    end case;

  end if;

end process Flintstones_SM_Proc;

Notes on the State machine Implementation

For the most part, the Flintstones State Machine’s operation should be clear. A few points are worth noting, however:

1. The reset signal (Sync_Reset_n) is synchronized with Clock_In before being sent to the State Machine.
2. Barney and Wilma must also be synchronous to Clock_In; at the very least, there must be an assurance that the State Machine’s state and output regis- ter’s setup and hold times are not violated.
3. This design assigns a default value to each output and to the state variable before entering the case statement. This ensures that only those signals that are not taking default (usually inactive) values need be listed in the case statement. This is optional; it is entirely reasonable to list every signal under each transition term, including inactive signals.
4. Note that the output signal Fred comes directly from a D-type flip-flop: it is not a decode of the state variable. This ensures Fred’s cleanliness (so to speak).
5. The “when others” in the case statement handles the possibility that the State Machine might end up in a dead state.

The code examples in this tutorial should be considered as examples only. There are many ways to code excellent VHDL; this code is a place to start. If you have a neat snippet of VHDL to add to the list, then please post your valuable comments below.

Tips for Implementing State Machine

At a low level of abstraction, a protocol is often most easily understood as a state machine. Design criteria can also easily be expressed in terms of desirable or undesirable protocol states and state transitions. In a way, the protocol state symbolizes the assumptions that each process in the system makes about the others. It defines what actions a process is allowed to take, which events it expects to happen, and how it will respond to those events.

The Xcell Journel Issue 81 gives some important tips on implementing state machines in your FPGA

Link to Xcell Journel issue 81

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Finite State Machine (FSM) Coding In Verilog

There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.

Verilog Code for FSM:
// 4-State Moore state machine
// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes.  (State
// transitions are synchronous.)
module seq_dect
(
    input    clk, data_in, reset,
    output reg  data_out
);
    // Declare state register
    reg        [2:0]state;
    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;

    // Determine the next state
    always @ (posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            case (state)
                S0:
                    if (data_in)
                        state <= S1;
                    else
                        state <= S0;
                S1:
                    if (data_in)
                        state <= S1;
                    else
                        state <= S2;
                S2:
                    if (data_in)
                        state <= S3;
                    else
                        state <= S2;
                S3:
                    if (data_in)
                        state <= S4;
                    else
                        state <= S2;
                S4:
                    if (data_in)
                        state <= S1;
                    else
                        state <= S2;
            endcase // case (state)
    end // always @ (posedge clk or posedge reset)
    // Output depends only on the state
    always @ (state) begin
        case (state)
            S0:
                data_out = 1'b0;
            S1:
                data_out = 1'b1;
            S2:
                data_out = 1'b0;
            S3:
                data_out = 1'b1;
            S4:
                data_out = 1'b1;               
            default:
                data_out = 1'b0;
        endcase // case (state)
    end // always @ (state)

endmodule // moore_mac

Finite State Machine (FSM) Coding In VHDL

There is a special Coding style for State Machines in VHDL as well as in Verilog.

Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.

 VHDL Code for FSM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Sequence detector for detecting the sequence "1011".
--Overlapping type.
entity seq_det is
port(   clk   : in std_logic;      --clock signal
        reset : in std_logic;      --reset signal
        S_in  : in std_logic;      --serial bit Input sequence   
        S_out : out std_logic);    -- Output        
end seq_det;
architecture Behavioral of seq_det is
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
begin
-- Synchronous Process
process(clk)
begin
    if( reset = '1' ) then                 --Synchronous Reset
        Current_State <= 'S0';
    elsif (clk'event and clk = '1') then   --Rising edge of Clock
        Current_State <= Next_State
    end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
    begin
        case Current_State is
            when S0 =>                     
                S_out <= '0';
                if ( s_in = '0' ) then
                    Next_State <= S0;
                else   
                    Next_State <= S1;
                end if;
            when S1 =>
                S_out <= '1';  
                if ( S_in = '0' ) then
                    Next_State <= S3;
                else   
                    Next_State <= S2;
                end if;
            when S2 =>
                S_out <= '0';  
                if ( S_in = '0' ) then
                    Next_State <= S0;
                else   
                    Next_State <= S3;
                end if;
            when S3 =>
                S_out <= '1';  
                if (S_in = '0' ) then
                    Next_State <= S2;
                else   
                    Next_State <= S4;
                end if;
            when S4 =>
                S_out <= '1';  
                if ( S_in = '0' ) then
                    Next_State <= S2;
                else   
                    Next_State <= S1;
                end if;
            when others =>
                NULL;
        end case;
    end if;
end process;