Magic - The VLSI Layout Editor, Extraction, and DRC Tool.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

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Xilinx ISE Design suite 10.1

Xilinx Integrated Software Environment (ISE) is a powerful yet flexible integrated design environment that allows you to design Xilinx FPGA and CPLD devices from start to finish. ISE includes our world class design entry, synthesis and implementation tools delivering the industry's fastest place and route times, highest performance, and most advanced design methodologies.

Project Navigator is the user interface that helps you manage the entire design process including design entry, simulation, synthesis, implementation and finally download the configuration of your FPGA or CPLD device.

The following is an outline of the features offered in ISE.

Design Entry

• HDL Editor
• StateCAD State Machine Editor
• Schematic Editor - Engineering Capture System (ECS)
• CORE Generator

Synthesis

• XST - Xilinx Synthesis Technology
• Integration with LeonardoSpectrum from Mentor Graphics, Inc.
• Integration with Synplify from Synplicity, Inc.

Simulation

• HDL Bencher Testbench Generator
• Integration with ModelSim Simulator from Model Technology, Inc.

Implementation

• Translate
• MAP
• Place and Route (PAR)
• Floorplanner
• FPGA Editor
• Timing Analyzer
• XPower
• Fit (CPLD only)
• Chipviewer (CPLD only)

Device Download and Program File Formatting

• BitGen
• iMPACT

Download the Xilinx ISE 10.1 design suit from Here

Transaction Layer (TL) of PCI Express

This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. On the transmit side, the Transaction Layer receives request data (such as “read from BIOS location FFF0h”) or completion data (“here is the result of that read”) from the device core, and then turns that information into an outgoing PCI Express transaction. On the receive side, the Transaction Layer also accepts incoming PCI Express transactions from its Data Link Layer (refer to fig.). This layer assumes all incoming information is correct, because it relies on its Data Link Layer to ensure that all incoming information is error-free and properly ordered.

AMD and Intel Announce Settlement of All Antitrust and IP Disputes

Intel Corporation and Advanced Micro Devices (NYSE: AMD) today announced a comprehensive agreement to end all outstanding legal disputes between the companies, including antitrust litigation and patent cross license disputes.

In a joint statement the two companies commented, "While the relationship between the two companies has been difficult in the past, this agreement ends the legal disputes and enables the companies to focus all of our efforts on product innovation and development."

Under terms of the agreement, AMD and Intel obtain patent rights from a new 5-year cross license agreement, Intel and AMD will give up any claims of breach from the previous license agreement, and Intel will pay AMD $1.25 billion. Intel has also agreed to abide by a set of business practice provisions. As a result, AMD will drop all pending litigation including the case in U.S. District Court in Delaware and two cases pending in Japan. AMD will also withdraw all of its regulatory complaints worldwide. The agreement will be made public in filings with the Securities and Exchange Commission.

http://www.amd.com/us/press-releases/Pages/amd-press-release-2009nov12.aspx

ELECTRIC VLSI Design Software

The Electric^TM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:

• Custom IC Layout
• Schematic Capture (Digital and Analog)
• Textual Languages such as VHDL and Verilog
• ....and much more.

The Electric VLSI Design System is a highly flexible and powerful system that can handle many different types of circuit design (MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc.) It handles geometry at any angle (not just Manhattan) and can even handle curves.

Layout is done by placing and wiring electrical components. Although this is standard practice for schematics, it is unusual for chip layout. However, because of this style of design, Electric understands chip layout at a more sophisticated level, and can aid in design to an unprecedented degree.

Electric has many analysis tools, including design-rule checking, simulation, and network comparison. Electric has many synthesis tools, including routing, compaction, silicon compilation, PLA generation, and compensation.

The user interface is quite sophisticated and runs on all popular workstations (Windows, Macintosh, and UNIX). It also provides interpretive languages for advanced users.

The software is freely available at www.staticfreesoft.com

VLSI Interview Questions-1

1. what is the difference between mealy and moore state-machines
2. how to solve setup and hold violations in the design
3. what is antenna violation & ways to prevent it
4. we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
5. what is tie-high and tie-low cells and where it is used
6. what is the difference between latches and flip-flops based designs
7. what is High-Vt and Low Vt cells
8. what is LEF mean?
9. what is DEF mean?
10. steps involved in designing an optimal padring
11. what is metastability and steps to prevent it
12. what is local-skew, global skew and useful skew
13. what are the various timing-paths which i should take care in my STA runs?
14. what are the various components of leakage-power
15. what are the various yield losses in the design
16. what is meant by virtual clock definition and why do i need it
17. what are the various variations which impacts timing of the design
18. what are the various Design constraints used, while performing synthesis for a design
19. specify few verilog constructs which are not supported by the synthesis tool
20. what are the various capacitances with an MOSFET?
21. Vds-Ids curve for an MOSFET, with increasing Vgs
22. explain basic operation of an MOSFET
23. what is channel length modulation
24. what is body effect
25. what is latchup in CMOS design and ways to prevent it?
26. what are the various design changes you do to meet design power targets
27. what is meant by library characterization
28. what is meant by wireload model
29. what are the measures to be taken to design for optimized area
30. what all will you be thinking while performing floorplan
31. what are the measures in the design taken for meeting signal integrity targets
32. what are the measures taken in the Design achieving better yield
33. what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
34. what are the steps incorporated for Engineering Change order[ECO]
35. what are the steps performed to achieve Lithography friendly Design
36. what does synthesis mean?
37. what are the pre-requistes to perform synthesis
38. can you explain the synthesis flow
39. what are the various ways to reduce clock insertion delay in the design
40. what are the various functional verification methodologies
41. what does formal verification mean
42. how will you time the output path in STA
43. how will you time the input path in STA
44. what is false path mean in STA and in what scenarios falsepath can come
45. what does multicycle path mean in STA and in what scenarios MCP can come
46. what are source synchronous paths in STA
47. Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it.
48. we have multiple instances in RTL, do you do anything special during synthesis stage
49. what do you call an event and when do you call an assertion.
50. what is difference between FPGA and ASIC.

Solutions to these questions will be provided on request.

mail to : info@vlsiencyclopedia.com

A typical analog design flow

In case of analog design, the flow changes somewhat.

=>Specifications=> Architecture =>Circuit Design =>SPICE Simulation =>Layout =>Parametric Extraction / Back Annotation =>Final Design =>Tape Out to foundry.

While digital design is highly automated now, very small portion of analog design can be automated. There is a hardware description language called AHDL but is not widely used as it does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs. This is true for small transistor count chips such as an operational amplifier, or a filter or a power management chip. For more complex analog chips such as data converters, the design is done at a transistor level, building up to a cell level, then a block level and then integrated at a chip level. Not many CAD tools are available for analog design even today and thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog as well as digital design.

From above discussion n from my personal experience i feel that digital design is the most important aspect of the VLSI design flow. Think if your design has some bug...!! the whole process then is costing billions of $. So it's very essential to take care start from the initial phase of designing.

Here during our discussion further we will go through several important concepts of digital dsigning and also see some standard designs.