ISRO Builds India's Fastest Supercomputer

Indian Space Research Organisation has built a supercomputer, which is to be India's fastest supercomputer in terms of theoretical peak performance of 220 TeraFLOPS (220 Trillion Floating Point Operations per second). The supercomputing facility named as Satish Dhawan Supercomputing Facility is located at Vikram Sarabhai Space Centre (VSSC), Thiruvananthapuram. The new Graphic Processing Unit (GPU) based supercomputer named "SAGA-220" (Supercomputer for Aerospace with GPU Architecture-220 TeraFLOPS) is being used by space scientists for solving complex aerospace problems. The supercomputer SAGA-220 was inaugurated by Dr K Radhakrishnan, Chairman, ISRO today at VSSC.

"SAGA-220" Supercomputer is fully designed and built by Vikram Sarabhai Space Centre using commercially available hardware, open source software components and in house developments. The system uses 400 NVIDIA Tesla 2070 GPUs and 400 Intel Quad Core Xeon CPUs supplied by WIPRO with a high speed interconnect. With each GPU and CPU providing a performance of 500 GigaFLOPS and 50 GigaFLOPS respectively, the theoretical peak performance of the system amounts to 220 TeraFLOPS. The present GPU system offers significant advantage over the conventional CPU based system in terms of cost, power and space requirements. The total cost of this Supercomputer is about Rs. 14 crores. The system is environmentally green and consumes a power of only 150 kW. This system can also be easily scaled to many PetaFLOPS (1000 TeraFLOPS).

Dynamic Timing Analysis

Dynamic timing analysis verifies circuit timing by applying test vectors to the circuit. This approach is an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths.

The most common dynamic timing analysis is the so-called min-max analysis method. Under min-max timing analysis, both minimum and maximum delays of circuit components are used to generate outputs, which are ranges (the spread of earliest data and latest arrival data) instead of edges. Since outputs are in turn fed into inputs, managing the ranges (merging them) can become very complex. As can be seen, if both min version & max version of the delays must be used, the simulation speed will be extremely slow.

Another major issue with dynamic timing analysis is the incomplete coverage. It may only check circuitry that is exercised by test stimulus, which may leave critical paths untested, and timing problems undiscovered. It is also not path oriented. Since dynamic timing analysis reports errors on a certain pin at a certain time, the user must trace through the schematic to locate the path that caused the problem (difficult for large designs).

Finally this method requires development time for test vectors. Dynamic timing analysis tools often track more information than logic simulators, making their performance slower. Also each component must contain both timing information and a functional model before timing verification can proceed. This could prevent the use of new parts that do not have functional models.

It should be noted that min-max simulation is not currently used in the industry. Instead, either functional simulation with timing (timing simulation) or formal verification method is typically used to verify complex IC designs. Typically people use the max version of delays to verify the circuit works under worst-case timing (no setup issues) and min version of the delays to verify best-case timing (no hold issues).

Advantages:
1. Extends coverage of circuit simulation (edges to region).
2. Evaluates worst-case timing using both min. and max. delay values for components.
3. Uses the same test stimulus as logic simulation.
4. Does not report false errors.

Disadvantages:
1. It is not complete.
2. It is not path oriented.
3. It is slower than logic simulation and may require additional test stimulus.
4. It requires functional behavioral models.

Dynamic timing analysis extends logic simulation by reporting violations in terms of simulation times and states. To test circuit timing using worst-case conditions, dynamic timing analysis evaluates the circuit using minimum and maximum propagation delays for each component for each component in the design.

Since dynamic timing analysis performs a simulation, it can use the same stimulus as a logic simulation. Because the stimulus functionally exercises the design, false errors of unused or uninteresting paths are not tested. Note a timing simulation reports results differently than a logic simulation. A logic simulation reports results as edge times and a timing simulation reports results as regions of ambiguity. The results of a timing simulation do not specify exactly when an event occurs, they specify a range of time in which an event can occur.

Static Timing Analysis

Static timing analysis verifies circuit timing by “adding up propagation delays along paths between clocked elements” in a circuit. It checks the delays along each path against the specified timing constraints for each circuit path and reports any existing timing violations. Static timing analysis tools can determine and report timing statistics such as the total number of paths, delays for each path and the circuit’s most critical paths. As design complexity increases, performing timing analysis manually becomes extremely difficult and sometimes even impossible. With increasing popularity of HDL based design methodologies, static timing analysis becomes increasingly popular among digital logic designers. To summarize, both static and dynamic timing analysis methods offer tradeoffs. One is not a replacement for the other. However, the static timing analysis method offers more complete coverage, little overhead, and the ability to report errors in terms of the design schematic.

Advantages:
1.It resembles manual analysis methods.
2. It is path oriented and finds all setup and hold violations.
3. It does not require stimulus or functional models.
4. It is faster than simulation. (for the same amount of coverage).

Disadvantages:
1. It can report false errors.
2. It cannot detect timing errors related to logical operation.

Static timing analysis is similar to manual analysis process, except that it is automated. This allows the design to be analyzed much faster. This makes it possible for a designer to experiment with different synthesis options and constraints in a short time. This method is also complete because it traces and evaluates all paths in a design, not just those exercised by test stimulus.

Because static timing analysis does not perform logic simulation, test stimulus and functional models are not required. This makes static analysis available earlier since development time for stimulus and models are not required.

The modeling requirements for a static analysis tool are relatively simple. However, timing information for each component in the design is required and the designer must specify waveform information about the input data and clock signals the design uses. The component timing information can be found in parts libraries or data books. Such timing information typically include: pin-to-pin delays, setup, hold time specifications and signal inversion information, and clock frequency constraints. Clock and data waveforms are a normal requirement of the design process, and do not require additional development time.

The major drawback of a static timing analysis tool is that it reports false errors. By checking all possible paths in a design, static timing analysis ensures that all possible setup and hold violations in the circuit have been found. However, the potential to detect some false errors exists since circuit behavior is not considered during the analysis. Static analysis tools cannot detect timing errors related to logical operation. Because static timing analysis does not perform functional testing, it cannot detect timing errors, such as race conditions, that are based on the logical operation of the circuit.

Difference between Static and Dynamic timing analysis

Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. The problem is that the simulations vector not can guarantee 100% coverage. The goal for the dynamic analysis is to get a 100% coverage. Dynamic timing simulation is still preferred for non-synchronous logic style. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.

Static timing analysis on the other hand check all path in the circuit even the false paths. False paths are paths that are not possible or interesting in actual operation of the circuit. Therefore you can say that static analysis starts above 100% and works towards 100% by detecting and excluding the false paths. Static tools have made major advancements in recent years, in fact all synthesis tools use static timing analysis internally. Something good about this approach is that almost all tools using it supports multi-cycle paths, in which a path delay constraint exceeds a single clock period. Everything isn't just good, many static timing tools have problems with feedback loops.

Read more ....

Timing Analysis

Depending on the design methodologies used, three types of timing analysis methods are commonly used:

1. Manual analysis
2. Static timing analysis
3. Dynamic timing analysis

Latch based designs are not common in large-scale integration; a separate section latch based static timing analysis which will be covered in later posts.

Manual Analysis: Manual analysis consists of taking a schematic or a netlist to determine the times signals arrive or leave at the input and output ports of the design, and calculating the delay time for the path by adding up the delay times for each component in the path. The objective of the process is to ensure that all signals meet the circuit constraints. This method works well for simple circuits and it is undesirable for large or iterative design process.

Static Timing Analysis: Static timing analysis verifies circuit timing by adding up propagation delays along paths between clocked elements in a circuit. It checks the delays along each path against the specified timing constraints for each circuit path and reports any existing timing violations. Static timing analysis tools can determine and report timing statistics such as the total number of paths, delays for each path and the circuit’s most critical paths...... Read more

Dynamic Timing Analysis: Dynamic timing analysis verifies circuit timing by applying test vectors to the circuit. This approach is an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths...... Read more

VHDL code for AND gate

 

library ieee;
use ieee.std_logic_1164.all;

entity my_and is

  port (a, b : in  std_logic;
        c    : out std_logic);

end my_and;

architecture my_and_arc of my_and is

  begin
  c <= a and b;

end my_and_arc;

Positive and Negative Edge Detector Circuit

Positive and negative edge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered events on certain GPIO inputs. Here i will show you a simple circuit which is use to detect Positive as well negative edges.

VHDL CODE : 

library ieee;
use ieee.std_logic_1164.all;
entity edge is
   port (
    inp        : in  std_logic;         -- inpit
    clk        : in  std_logic;         -- clock
    rst        : in  std_logic;         -- reset
    edge_op : out std_logic);        -- setected edge output
 end edge;

architecture edge_ar of edge is
  signal sig1 : std_logic;              -- signal from 1st flop
  signal sig2 : std_logic;              -- signal from 2nd flop

begin  -- edge_ar
   edge : process(clk, rst)
  begin
    if rst = '1' then
      sig1 <= '0';
      sig2 <= '0';
    elsif clk'event and clk = '1' then
      sig1 <= inp;
      sig2 <= sig1;
    end if;
  end process edge;

  edge_op <= sig1 xor sig2;

end edge_ar;