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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Tuesday, 5 July 2011

Synchronous “up/down” Counter

We can build a counter circuit with selectable between "up" and "down" count modes by having dual lines of AND gates detecting the appropriate bit conditions for an "up" and a "down" counting sequence, respectively, then use OR gates to combine the AND gate outputs to the J and K inputs of each succeeding flip-flop:

4_bit_Synchronous_up_down_counter

This circuit isn't as complex as it might first appear. The Up/Down control input line simply enables either the upper string or lower string of AND gates to pass the Q/Q' outputs to the succeeding stages of flip-flops. If the Up/Down control line is "high," the top AND gates become enabled, and the circuit functions exactly the same as the first ("up") synchronous counter circuit shown in this section. If the Up/Down control line is made "low," the bottom AND gates become enabled, and the circuit functions identically to the second ("down" counter) circuit shown in this section.

To illustrate, here is a diagram showing the circuit in the "up" counting mode (all disabled circuitry shown in grey rather than black):

4_bit_Synchronous_up_down_counter_count_up_mode 

Here, shown in the "down" counting mode, with the same grey coloring representing disabled circuitry:

4_bit_Synchronous_up_down_counter_count_down_mode

Links:

Different type of synchronous counters

A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time.

In electronics, synchronous counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:

Binary counters

Binary counters are the simplest form of counters. An N-bit binary counter counts from 0 to (2N - 1) and back to 0 again.

binary_synchronous_counter

 

Links:

  • Different types of counters
  • Up/down counters
  • Loadable counters
  • BCD counters
  • Ring counters
  • Johnson counters

  • Why “synchronous”?

    • The difference between asynchronous and synchronous counters.

    In an asynchronous counter, an external event is used to directly SET or CLEAR a flip-flop when it occurs. In a synchronous counter however, the external event is used to produce a pulse that is synchronised with the internal clock. An example of an asynchronous counter is a ripple counter. Each flip-flop in the ripple counter is clocked by the output from the previous flip-flop. Only the first flip-flop is clocked by an external clock. Below is an example of a 4-bit ripple counter.

    4_bit_asynchronous_counter

    • Dangers of asynchronous counters.

    Although the asynchronous counter is easier to implement, it is more "dangerous" than the synchronous counter. In a complex system, there are many state changes on each clock edge, and some IC's (integrated circuits) respond faster than others. If an external event is allowed to affect a system whenever it occurs, a small percentage of the time it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. What is worse, these problems are difficult to test for and difficult to foresee because of the random time difference between the events.

     

    Links:

    Monday, 4 July 2011

    Why do we need counters ?

    In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting.

    A timing problem might require that a high-frequency pulse train, such as the output of a 10-MHz crystal oscillator, be divided to produce a pulse train of a much lower frequency, say 1 Hz. This application is required in a precision digital clock, where it is not possible to build a crystal oscillator whose natural frequency is 1 Hz.

    State_machine_of_a_BCD_CounterA sequencing problem would arise if, for instance, it became necessary to apply power to various components of a large machine in a specific order. The starting of a rocket motor is an example where the energizing of fuel pumps, ignition, and possibly explosive bolts for staging must follow a critical order.

    Measuring the flow of auto traffic on roadway is an application in which an event (the passage of a vehicle) must increment a tally. This can be done automatically with an electronic counter triggered by a photocell or road sensor. In this way, the total number of vehicles passing a certain point can be counted.

    Links:

    Synchronous Counter

    The purpose of writing this is to collate information on Digital Synchronous Counters. Particular emphasis was placed on the following areas :

    1. Types of Synchronous Counters and How they work

    2. Fast Counter Techniques

    3. Implementation of Counters :

    4. Dedicated Hardware and Alternative Devices

    According to the Oxford Encyclopædic Dictionary:

    synchronous adj. existing or occurring at the same time.

    counter n. an apparatus used for counting. || a person or thing that counts.

    So a "synchronous counter" should mean "a person, thing or apparatus that counts at the same time" ?!?! Hmmm...

    Let us take a look at the definition given by the IBM Dictionary of Computing instead.

    synchronous (1) Pertaining to two or more processes that depend upon the occurrence of specific events such as common timing signals. (2) Occurring with a regular or predictable time relationship.

    counter (1) A functional unit with a finite number of states each of which represents a number that can be, upon receipt of an appropriate signal, increased by unity or by a given constant. This device is usually capable of bringing the represented number to a specified value; for example zero.

    So a "synchronous counter" is actually a functional unit with a certain number of states, each representing a number which can be increaced or decreased upon receiving an appropriate signal (e.g. a rising edge pulse), and is usually used to count to, or count down to zero from, a specified number N.

    ... and what it "really" means. OK! Enough of dictionary definitions.

    Basically, any sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses, called count pulses, may be clock pulses or they may originate from an external source and may occur at prescribed intervals of time or at random. The sequence of states in a counter may follow a binary count or any other sequence.

    Counter_State_Maching

     

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    Sunday, 3 July 2011

    VLSI FPGA Projects Topics Using VHDL/Verilog

      1. 8-bit Micro Processor

      2. RISC Processor in VLDH

      3. Floating Point Unit

      4. LFSR - Random Number Generator

      5. Versatile Counter

      6. RS232 interface

      7. I2C Slave

      8. 8b10b Encoder/Decoder

      9. Floating Point Adder and Multiplier

      10. Progressive Coding For Wavelet-Based Image Compression

      11. An Area-Efficient Universal Cryptography Processor for Smart Cards

      12. FPGA Based Power Efficient Channelizer for Software Defined Radio

      13. Implementation of IEEE 802.11a WLAN baseband Processor using FPGA with Verilog/VHDL code

      14. FPGA Implementation of USB Transceiver Macrocell Interface with Usb2.0 Specifications

      15. Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFIC

      16. Superscalar Power Efficient Fast Fourier Transform FFT Architecture

      17. High-Speed Architecture for Reed-Solomon Decoder/Encoder

      18. Fault Secure Encoder and Decoder for Nano-memory Applications

      19. Implementation Huffman Coding For Bit Stream Compression In Mpeg – 2

      20. Implementation of Hash Algorithm Used for Cryptography And Security

      21. Implementation of Scramblers and Descramblers in Fiber Optic Communication Systems – SONET and OTN

      22. Implementation of Matched Filters Frequency Spectrum in Code Division Multiple Access (CDMA) System and its Implementation

      23. High Definition HDTV Data Encoding and Decoding using Reed Solomon Code

      24. Design & Implementation of Noise / Echo canceler using FPGA with Verilog/VHDL

      25. A VLSI Architecture for Visible Watermarking In A Secure Still Digital Camera (S2dc) Design

      26. FPGA-Based Architecture for Real Time Image Feature Extraction

      27. Implementation of Lossless Data Compression and Decompression using (Parallel Dictionary Lempel Ziv Welch) PDLZW Algorithm

      28. 8/16/32 Point Fast Fourier Transform Algorithm using FPGA with Verilog/VHDL

      29. VLSI Implementation of Booths Algorithm using FPGA with Verilog/VHDL

      30. Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICs

      31. VLSI implementation of Cascaded-Integrator-Comb Filter

      32. VLSI implementation of Wave-Digital-Filters

      33. VLSI implementation of Notch filters

      34. VLSI implementation of fractional sample rate converter (FSRC) and corresponding converter architecture

      35. VLSI implementation of canonical Huffman encoder/decoder algorithm using FPGA with Verilog/VHDL code

      36. VLSI implementation of RC5 Encryption/Decryption Algorithm

      37. VLSI implementation of Steganography using FPGA with Verilog/VHDL code

      38. VLSI implementation of 16 Bit fixed point DSP Processor using FPGA with Verilog/VHDL

      39. VLSI Implementation of Address Generation Coprocessor

      40. VLSI Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm

      41. Implementation of LZW Data Compression Algorithm.

      42. A Low Power VLSI Implementation for JPEG2000 Codec using FPGA with Verilog/VHDL

      43. A Verilog Implementation of Built In Self Test of UART

      44. Fuzzy based PID Controller using VHDL for Transportation Application

      45. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication

      46. Scalable multi gigabit pattern matching for packet inspection

      47. An FPGA-based Architecture for Real Time Image Feature Extraction

      48. Synchronization in Software Radios – Carrier and Timing Recovery Using FPGAs

      49. Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

      50. High-Speed Booth Algorithm Encoded Parallel Multiplier Design

      51. Implementation of IEEE 802.11a WLAN Baseband Processor

      52. MPEG-4 AVClH.264 Transform Coding Design using FPGA with Verilog/VHDL

      53. FPGA based Generation of High Frequency Carrier for Pulse Compression using CORDIC Algorithm

      54. Watermarking in a Secure Still Digital Camera Design

      55. DCT/IDCT Algorithms Implemented in FPGA Chips for Real-Time Image Compression

      56. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication

      57. Robust Image Watermarking Based on Multiband Wavelets and Empirical Mode Decomposition

      58. A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design

      59. VLSI Design & Implementation of Cryptography AES/DES Encryption Algorithm using FPGA with Verilog/VHDL code

      60. VLSI Design & Implementation of Viterbi Algorithm-Encoder/Decoder using FPGA with Verilog/VHDL code

      61. VLSI Design & Implementation of DDRR Algorithm using FPGA with Verilog/VHDL code

      62. VLSI Design & Implementation of Dynamic/Deficit Round Robin Algorithm using FPGA with Verilog/VHDL code

      63. VLSI Design & Implementation of Watermarking Algorithm using FPGA with Verilog/VHDL code

      64. VLSI Design & Implementation of Secure transmitting and receiving text data in communication systems using FPGA with Verilog/VHDL code

      65. VLSI Design & Implementation of UART Asynchronous Transmitter/Receiver using FPGA with Verilog/VHDL code

      66. VLSI Design & Implementation of RS-232 Transmitter/Receiver using FPGA with Verilog/VHDL code

      67. VLSI Design & Implementation of Asynchronous Serial controller using FPGA with Verilog/VHDL code

      68. VLSI Design & Implementation of Universal Serial Bus USB Device Controller using FPGA with Verilog/VHDL code

      69. VLSI Design & Implementation of GPS-GSM based Home Automation System using FPGA with Verilog/VHDL code

      70. VLSI Design & Implementation of 16/32/64-bit Low Power RISC/CISC Processor using FPGA with Verilog/VHDL code

      71. VLSI Design & Implementation of Multichannel I2S Audio Controller using FPGA with Verilog/VHDL code

      72. VLSI Design & Implementation of Asynchronous FIFO using FPGA with Verilog/VHDL code

      73. VLSI Design & Implementation of AHB Master/Slave using FPGA with Verilog/VHDL code

      74. VLSI Design & Implementation of AMBA AHB to PVCI Bridge using FPGA with Verilog/VHDL code

      75. VLSI Design & Implementation of Huffman Encoder/Decoder using FPGA with Verilog/VHDL code

      76. VLSI Design & Implementation of Programmable 16-Tap FIR Filter using FPGA with Verilog/VHDL code

      77. VLSI Design & Implementation of 2-D Convolution Engine using FPGA with Verilog/VHDL code

      78. VLSI Design & Implementation of VGA/LCD Controller using FPGA with Verilog/VHDL code

      79. VLSI Design & Implementation of JTAG TAP controller using FPGA with Verilog/VHDL code

      80. VLSI Design & Implementation of Booth Multiplier using FPGA with Verilog/VHDL code

      81. VLSI Design & Implementation of Pipeline JPEG Encoder using FPGA with Verilog/VHDL code

      82. VLSI Design & Implementation of Cyclic Redundancy Check ECRC/LCRC Error Check using FPGA with Verilog/VHDL code

      83. VLSI Design & Implementation of Vehicle Tracking & Safety System using FPGA with Verilog/VHDL code

      84. VLSI Design & Implementation of Low Power FIR Filter using FPGA with Verilog/VHDL code

      85. VLSI Design & Implementation of Pattern Generator using FPGA with Verilog/VHDL code

      86. VLSI Design & Implementation of PCI Express using FPGA with Verilog/VHDL code

      87. VLSI Design & Implementation of Highspeed USB 2.0/Superspeed USB 3.0 Transmitter and Receiver using FPGA with Verilog/VHDL code

      88. VLSI Design & Implementation of Wishbone Controller using FPGA with Verilog/VHDL code

      89. VLSI Design & Implementation of PVCI Master/Slave using FPGA with Verilog/VHDL code

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