Choosing FPGA or DSP for your Application

 

FPGA or DSP - The Two Solutions

The DSP is a specialised microprocessor - typically programmed in C, perhaps with assembly code for performance. It is well suited to extremely complex maths-intensive tasks, with conditional processing. It is limited in performance by the clock rate, and the number of useful operations it can do per clock. As an example, a TMS320C6201 has two multipliers and a 200MHz clock – so can achieve 400M multiplies per second.

In contrast, an FPGA is an uncommitted "sea of gates". The device is programmed by connecting the gates together to form multipliers, registers, adders and so forth. Using the Xilinx Core Generator this can be done at a block-diagram level. Many blocks can be very high level – ranging from a single gate to an FIR or FFT. Their performance is limited by the number of gates they have and the clock rate. Recent FPGAs have included Multipliers especially for performing DSP tasks more efficiently. – For example, a 1M-gate Virtex-II™ device has 40 multipliers that can operate at more than 100MHz. In comparison with the DSP this gives 4000M multiplies per second.

 

Where They Excel

When sample rates grow above a few Mhz, a DSP has to work very hard to transfer the data without any loss. This is because the processor must use shared resources like memory busses, or even the processor core which can be prevented from taking interrupts for some time. An FPGA on the other hand dedicates logic for receiving the data, so can maintain high rates of I/O.

A DSP is optimised for use of external memory, so a large data set can be used in the processing. FPGAs have a limited amount of internal storage so need to operate on smaller data sets. However FPGA modules with external memory can be used to eliminate this restriction.

A DSP is designed to offer simple re-use of the processing units, for example a multiplier used for calculating an FIR can be re-used by another routine that calculates FFTs. This is much more difficult to achieve in an FPGA, but in general there will be more multipliers available in the FPGA. 

If a major context switch is required, the DSP can implement this by branching to a new part of the program. In contrast, an FPGA needs to build dedicated resources for each configuration. If the configurations are small, then several can exist in the FPGA at the same time. Larger configurations mean the FPGA needs to be reconfigured – a process which can take some time.

The DSP can take a standard C program and run it. This C code can have a high level of branching and decision making – for example, the protocol stacks of communications systems. This is difficult to implement within an FPGA.

Most signal processing systems start life as a block diagram of some sort. Actually translating the block diagram to the FPGA may well be simpler than converting it to C code for the DSP.

Making a Choice

There are a number of elements to the design of most signal processing systems, not least the expertise and background of the engineers working on the project. These all have an impact on the best choice of implementation. In addition, consider the resources available – in many cases, I/O modules have FPGAs on board. Using these with a DSP processor may provide an ideal split.

 

As a rough guideline, try answering these questions:

1. What is the sampling rate of this part of the system? If it is more than a few MHz, FPGA is the natural choice.
2. Is your system already coded in C? If so, a DSP may implement it directly. It may not be the highest performance solution, but it will be quick to develop.
3. What is the data rate of the system? If it is more than perhaps 20-30Mbyte/second, then FPGA will handle it better.
4. How many conditional operations are there? If there are none, FPGA is perfect. If there are many, a software implementation may be better.
5. Does your system use floating point? If so, this is a factor in favour of the programmable DSP. None of the Xilinx cores support floating point today, although you can construct your own.
6. Are libraries available for what you want to do? Both DSP & FPGA offer libraries for basic building blocks like FIRs or FFTs. However, more complex components may not be available, and this could sway your decision to one approach or the other.

In reality, most systems are made up of many blocks. Some of those blocks are best implemented in FPGA, others in DSP. Lower sampling rates and increased complexity suit the DSP approach; higher sampling rates, especially combined with rigid, repetitive tasks, suit the FPGA.

 

Some Examples

Here are a few examples of signal processing blocks, along with how we would implement them:

1. First decimation filter in a digital wireless receiver. Typically, this is a CIC filter, operating at a sample rate of 50-100MHz. A 5-stage CIC has 10 registers & 10 adds, giving an "add rate" of 500-1000MHz.
   At these rates any DSP processor would find it extremely difficult to do anything. However, the CIC has an extremely simple structure, and implementing it in an FPGA would be easy. A sample rate of 100MHz should be achievable, and even the smallest FPGA will have a lot of resource left for further processing.
2. Communications Protocol Stack – ISDN, IEEE1394 etc; these are complex large pieces of C code, completely unsuitable for the FPGA. However the DSP will implement them easily. Not only that, a single code base can be maintained, allowing the code stack to be implemented on a DSP in one product, or a separate control processor in another; and bringing the opportunity to licence the code stack from a specialist supplier.
3. Digital radio receiver – baseband processing. Some receiver types would require FFTs for signal acquisition, then matched filters once a signal is acquired. Both blocks can be easily implemented by either approach. However, there is a mode change – from signal acquisition to signal reception.
   It may well be that this is better suited to the DSP, as the FPGA would need to implement both blocks simultaneously. Note that the RF processing is better in an FPGA, so this is likely to be a mixed system.
   (Note – with today’s larger FPGAs, both modes of this system could be included in the FPGA at the same time.)
4. Image processing. Here, most of the operations on an image are simple and very repetitive – best implemented in an FPGA. However, an imaging pipeline is often used to identify "blobs" or "Regions of Interest" in an object being inspected. These blobs can be of varying sizes, and subsequent processing tends to be more complex. The algorithms used are often adaptive, depending on what the blob turns out to be… so a DSP-based approach may be better for the back end of the imaging pipeline.

Summary

FPGA and DSP represent two very different approaches to signal processing – each good at different things. There are many high sampling rate applications that an FPGA does easily, while the DSP could not. Equally, there are many complex software problems that the FPGA cannot address.

MIT engineers Innovates an “Intelligent co-pilot” for cars

IT engineers have developed a semi-autonomous vehicle safety system that takes over if the driver does something stupid.

The system uses an onboard camera and laser rangefinder to identify hazards. An algorithm analyzes the data and identifies safe zones — avoiding, for example, barrels in a field, or other cars on a roadway.
The driver's in charge - until the system recognizes that the vehicle's about to exit a safe zone and takes over.

"The real innovation is enabling the car to share [control] with you," says PhD student Sterling Anderson. "If you want to drive, it’ll just make sure you don’t hit anything."

The team's approach is based on identifying safe zones, or 'homotopies', rather than specific paths of travel. Instead of mapping out individual paths along a roadway, the researchers divide a vehicle’s environment into triangles, with certain 'constrained' triangle edges representing an obstacle or a lane’s boundary.

If a driver looks like crossing a constrained edge — for instance, if he’s fallen asleep at the wheel and is about to run into a barrier  — the system takes over, steering the car back into the safe zone.

The system works well in tests, say its designers: in more than 1,200 trials of the system, with , there have only been a few collisions, mostly when glitches in the vehicle’s camera failed to identify an obstacle.

One possible problem with the system, though, is that it could give drivers a false sense of confidence on their own abilities.

Using it, says Anderson, "You’d say, ‘Hey, I pulled this off,’ and you wouldn’t know that the car is changing things behind the scenes to make sure the vehicle remains safe, even if your inputs are not."

He and Iagnemma are now exploring ways to tailor the system to various levels of driving experience.

They're also hoping to pare down the system to identify obstacles using a single cellphone.

"You could stick your cellphone on the dashboard, and it would use the camera, accelerometers and gyro to provide the feedback needed by the system," says Anderson.

"I think we'll find better ways of doing it that will be simpler, cheaper and allow more users access to the technology."

8-bit Micro Processor

This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible computer. It very useful design which introduces most of the basic and fundamental ideas behind computer operation.

This design could be used for instruction classes for undergraduate classes or specific VHDL classes. This processor is based on the 8080 architecture, therefore, it could be upgraded step by step to integrate further facilities. It is very exciting challenge for the students to do so. Further, they could think about building complete system, i.e. integrating and I/O peripherals to the processor.

The design is proven for ASIC and FPGA. It was implemented using Xilinx FPGA Spartan-3E starter kit. A full documentation for the code and the used resources are attached within the project.

For project details please write to us on info@vlsiencyclopedia.com

Get free daily email updates!

Follow us!

Floating Point Adder and Multiplier

The FP Adder is a single-precision, IEEE-754 compliant, signed adder/substractor. It includes both single-cycle and 6-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 385 CLBs and with a theoretical maximum operating frequency of 6MHz for the single-cycle design and 87MHz for the pipelined design. The design was tested at 33MHz.

The FP Multiplier is a single-precision, IEEE-754 compliant, signed multiplier. It includes both single-cycle and 4-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 119 CLBs and with a theoretical maximum operating frequency of 8MHz for the single-cycle design and 90MHz for the pipelined design. The design was tested at 33MHz.

Features

- IEEE-754 compliant
- 32 bits, single precision
- Works with normalized and un-normalized numbers
- Simple block design, good for FP arithmetic learning
- Adder
- 385 CLBs
- 87 MHz, 6-stage pipelined
- Multiplier
- 119 CLBs
- 90 MHz, 4-stage pipelined

PROGRESSIVE CODING FOR WAVELET-BASED IMAGE COMPRESSION

Description of the Project:-

This paper describes the hardware design flow of lifting based 2-D Forward Discrete Wavelet Transform (FDWT) processor for JPEG 2000. In order to build high quality image of JPEG 2000 codec, an effective 2-D FDWT algorithm has been performed on input image file to get the decomposed image coefficients. The Lifting Scheme reduces the number of operations execution steps to almost one-half of those needed with a conventional convolution approach. Initially, the lifting based 2-D FDWT algorithm has been developed using Mat lab. The FDWT modules were simulated using XPS(8.1i) design tools. The final design was verified with Matlab image processing tools.

Comparison of simulation results Matlab was done to verify the proper functionality of the developed module. The motivation in designing the hardware modules of the FDWT was to reduce its complexity, enhance its performance and to make it suitable development on a reconfigurable FPGA based platform for VLSI implementation. Results of the decomposition for test image validate the design. The entire system runs at 215 MHz clock frequency and reaches a speed performance suitable for several realtime applications. The result of simulation displays that lifting scheme needs less memory requirement.

Introduction :
A majority of today’s Internet bandwidth is estimated to be used for images and video. Recent multimedia applications for handheld and portable devices place a limit on the available wireless bandwidth. The bandwidth is limited even with new connection standards. JPEG image compression that is in widespread use today took several years for it to be perfected. Wavelet based techniques such as JPEG2000 for image compression has a lot more to offer than conventional methods in terms of compression ratio. Currently wavelet implementations are still under development lifecycle and are being perfected. Flexible energy-efficient hardware implementations that can handle multimedia functions such as image processing, coding and decoding are critical, especially in hand-held portable multimedia wireless devices.

Background
Data compression is, of course, a powerful, enabling technology that plays a vital role in the information age. Among the various types of data commonly transferred over networks, image and video data comprises the bulk of the bit traffic. For example, current estimates indicate that image data take up over 40% of the volume on the Internet. The explosive growth in demand for image and video data, coupled with delivery bottlenecks has kept compression technology at a premium.
Among the several compression standards available, the JPEG image compression standard is in wide spread use today. JPEG uses the Discrete Cosine Transform (DCT) as the transform, applied to 8-by-8 blocks of image data. The newer standard JPEG2000 is based on the Wavelet Transform (WT). Wavelet Transform offers multi-resolution image analysis, which appears to be well matched to the low level characteristic of human vision. The DCT is essentially unique but WT has many possible realizations. Wavelets provide us with a basis more suitable for representing images.

This is because it cans represent information at a variety of scales, with local contrast changes, as well as larger scale structures and thus is a better fit for image data.

Aim of the project
The main aim of the project is to implement and verify the image compression technique and to investigate the possibility of hardware acceleration of DWT for signal processing applications. A hardware design has to be provided to achieve high performance, in comparison to the software implementation of DWT. The goal of the project is to

. Implement this in a Hardware description language (Here VHDL).
. Perform simulation using tools such as Xilinx ISE 8.1i.
. Check the correctness and to synthesize for a Spartan 3E FPGA Kit.

The STFT represents a sort of compromise between the time- and frequency-based views of a signal. It provides some information about both when and at what frequencies a signal event occurs. However, you can only obtain this information with limited precision, and that precision is determined by the size of the window.

While the STFT compromise between time and frequency information can be useful, the drawback is that once you choose a particular size for the time window, that window is the same for all frequencies. Many signals require a more flexible approach—one where we can vary the window size to determine more accurately either time or frequency.

Problem Present in Fourier Transform : The Fundamental idea behind wavelets is to analyze according to scale. Indeed, some researchers feel that using wavelets means adopting a whole new mind-set or perspective in processing data. Wavelets are functions that satisfy certain mathematical requirements and are used in representing data or other functions. This idea is not new. Approximation using superposition of functions has existed since the early 18OOs, when Joseph Fourier discovered that he could superpose sines and cosines to represent other functions.

However, in wavelet analysis, the scale used to look at data plays a special role. Wavelet algorithms process data at different scales or resolutions. Looking at a signal (or a function) through a large “window,” gross features could be noticed. Similarly, looking at a signal through a small “window,” small features could be noticed. The result in wavelet analysis is to see both the forest and the trees, so to speak.

This makes wavelets interesting and useful. For many decades scientists have wanted more appropriate functions than the sines and cosines, which are the basis of Fourier analysis, to approximate choppy signals.’ By their definition, these functions are non-local (and stretch out to infinity). They therefore do a very poor job in approximating sharp spikes. But with wavelet analysis, we can use approximating functions that are contained neatly in finite domains. Wavelets are well-suited for approximating data with sharp discontinuities.

The wavelet analysis procedure is to adopt a wavelet prototype function, called an analyzing wavelet or mother wavelet. Temporal analysis is performed with a contracted, high-frequency version of the prototype wavelet, while frequency analysis is performed with a dilated, low-frequency version of the same wavelet. Because the original signal or function can be represented in terms of a wavelet expansion (using coefficients in a linear combination of the wavelet functions), data operations can be performed using just the corresponding wavelet coefficients.

And if wavelets best adapted to data are selected, the coefficients below a threshold is truncated, resultant data are sparsely represented. This sparse coding makes wavelets an excellent tool in the field of data compression. Other applied fields that are using wavelets include astronomy, acoustics, nuclear engineering, sub-band coding, signal and image processing, neurophysiology, music, magnetic resonance imaging, speech discrimination, optics, fractals, turbulence, earthquake prediction, radar, human vision, and pure mathematics applications such as solving partial differential equations.

Basically wavelet transform (WT) is used to analyze non-stationary signals, i.e., signals whose frequency response varies in time, as Fourier transform (FT) is not suitable for such signals. To overcome the limitation of FT, short time Fourier transform (STFT) was proposed. There is only a minor difference between STFT and FT. In STFT, the signal is divided into small segments, where these segments (portions) of the signal can be assumed to be stationary. For this purpose, a window function "w" is chosen. The width of this window in time must be equal to the segment of the signal where its still be considered stationary. By STFT, one can get time-frequency response of a signal simultaneously, which can’t be obtained by FT.

Scaling
We’ve seen the interrelation of wavelets and quadrature mirror filters. The wavelet function  is determined by the high pass filter, which also produces the details of the wavelet decomposition.
There is an additional function associated with some, but not all wavelets. This is the so-called scaling function. The scaling function is very similar to the wavelet function. It is determined by the low pass quadrature mirror that iteratively up- sampling and convolving the high pass filter produces a shape approximating the wavelet function, iteratively up-sampling and convolving the low pass filter produces a shape approximating the scaling function.We’ve already alluded to the fact that wavelet analysis produces a time-scale view of a signal and now we’re talking about scaling and shifting wavelets.

What exactly do we mean by scale in this context?
Scaling a wavelet simply means stretching (or compressing) it. To go beyond colloquial descriptions such as “stretching,” we introduce the scale factor, often denoted by the letter a.

If we’re talking about sinusoids, for example the effect of the scale factor is very easy to see:

One-Stage Decomposition
For many signals, the low-frequency content is the most important part. It is what gives the signal its identity. The high-frequency content on the other hand imparts flavor or nuance. Consider the human voice. If you remove the high-frequency components, the voice sounds different but you can still tell what’s being said. However, if you remove enough of the low-frequency components, you hear gibberish. In wavelet analysis, we often speak of approximations and details. The approximations are the high-scale, low-frequency components of the signal. The details are the low-scale, high-frequency components. The filtering process at its most basic level looks like this:

The original signal S passes through two complementary filters and emerges as two signals. Unfortunately, if we actually perform this operation on a real digital signal, we wind up with twice as much data as we started with. Suppose, for instance that the original signal S consists of 1000 samples of data. Then the resulting signals will each have 1000 samples, for a total of 2000. These signals A and D are interesting, but we get 2000 values instead of the 1000 we had. There exists a more subtle way to perform the decomposition using wavelets.

RISC Processor

A small RISC CPU (written in VHDL) that is compatible with the 12 bit opcode PIC family. Single cycle operation normally, two cycles when the program counter is modified. Clock speeds of over 40Mhz are possible when using the Xilinx Virtex optimizations.
Licensed under LGPL.

The core has a single pipeline stage and is run from a single clock, so (ignoring program counter changes) a 40Mhz clock will give 40 MIPS processing speed. Any instruction which modifies the program counter, for example a branch or skip, will result in a pipeline stall and this will only cost one additional clock cycle.

The CPU architecture chosen is not particularly FPGA friendly, for example multiplexers are generally quite expensive. The maximum combinatorial path delay is also long, so to ease the place and route tool's job the core is written at a low level. It instantiates a number of library macros, for example a 4:1 mux. Two versions of these are given, one is generic VHDL and the second is optimized for Xilinx Virtex series (including Spartan devices).

VLSI FPGA Projects Topics Using VHDL/Verilog

1. 8-bit Micro Processor

2. RISC Processor in VLDH

3. Floating Point Unit

4. LFSR - Random Number Generator

5. Versatile Counter

6. RS232 interface

7. I2C Slave

8. 8b10b Encoder/Decoder

9. Floating Point Adder and Multiplier

10. Progressive Coding For Wavelet-Based Image Compression

11. An Area-Efficient Universal Cryptography Processor for Smart Cards

12. FPGA Based Power Efficient Channelizer for Software Defined Radio

13. Implementation of IEEE 802.11a WLAN baseband Processor using FPGA with Verilog/VHDL code

14. FPGA Implementation of USB Transceiver Macrocell Interface with Usb2.0 Specifications

15. Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFIC

16. Superscalar Power Efficient Fast Fourier Transform FFT Architecture

17. High-Speed Architecture for Reed-Solomon Decoder/Encoder

18. Fault Secure Encoder and Decoder for Nano-memory Applications

19. Implementation Huffman Coding For Bit Stream Compression In Mpeg – 2

20. Implementation of Hash Algorithm Used for Cryptography And Security

21. Implementation of Scramblers and Descramblers in Fiber Optic Communication Systems – SONET and OTN

22. Implementation of Matched Filters Frequency Spectrum in Code Division Multiple Access (CDMA) System and its Implementation

23. High Definition HDTV Data Encoding and Decoding using Reed Solomon Code

24. Design & Implementation of Noise / Echo canceler using FPGA with Verilog/VHDL

25. A VLSI Architecture for Visible Watermarking In A Secure Still Digital Camera (S2dc) Design

26. FPGA-Based Architecture for Real Time Image Feature Extraction

27. Implementation of Lossless Data Compression and Decompression using (Parallel Dictionary Lempel Ziv Welch) PDLZW Algorithm

28. 8/16/32 Point Fast Fourier Transform Algorithm using FPGA with Verilog/VHDL

29. VLSI Implementation of Booths Algorithm using FPGA with Verilog/VHDL

30. Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICs

31. VLSI implementation of Cascaded-Integrator-Comb Filter

32. VLSI implementation of Wave-Digital-Filters

33. VLSI implementation of Notch filters

34. VLSI implementation of fractional sample rate converter (FSRC) and corresponding converter architecture

35. VLSI implementation of canonical Huffman encoder/decoder algorithm using FPGA with Verilog/VHDL code

36. VLSI implementation of RC5 Encryption/Decryption Algorithm

37. VLSI implementation of Steganography using FPGA with Verilog/VHDL code

38. VLSI implementation of 16 Bit fixed point DSP Processor using FPGA with Verilog/VHDL

39. VLSI Implementation of Address Generation Coprocessor

40. VLSI Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm

41. Implementation of LZW Data Compression Algorithm.

42. A Low Power VLSI Implementation for JPEG2000 Codec using FPGA with Verilog/VHDL

43. A Verilog Implementation of Built In Self Test of UART

44. Fuzzy based PID Controller using VHDL for Transportation Application

45. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication

46. Scalable multi gigabit pattern matching for packet inspection

47. An FPGA-based Architecture for Real Time Image Feature Extraction

48. Synchronization in Software Radios – Carrier and Timing Recovery Using FPGAs

49. Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

50. High-Speed Booth Algorithm Encoded Parallel Multiplier Design

51. Implementation of IEEE 802.11a WLAN Baseband Processor

52. MPEG-4 AVClH.264 Transform Coding Design using FPGA with Verilog/VHDL

53. FPGA based Generation of High Frequency Carrier for Pulse Compression using CORDIC Algorithm

54. Watermarking in a Secure Still Digital Camera Design

55. DCT/IDCT Algorithms Implemented in FPGA Chips for Real-Time Image Compression

56. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication

57. Robust Image Watermarking Based on Multiband Wavelets and Empirical Mode Decomposition

58. A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design

59. VLSI Design & Implementation of Cryptography AES/DES Encryption Algorithm using FPGA with Verilog/VHDL code

60. VLSI Design & Implementation of Viterbi Algorithm-Encoder/Decoder using FPGA with Verilog/VHDL code

61. VLSI Design & Implementation of DDRR Algorithm using FPGA with Verilog/VHDL code

62. VLSI Design & Implementation of Dynamic/Deficit Round Robin Algorithm using FPGA with Verilog/VHDL code

63. VLSI Design & Implementation of Watermarking Algorithm using FPGA with Verilog/VHDL code

64. VLSI Design & Implementation of Secure transmitting and receiving text data in communication systems using FPGA with Verilog/VHDL code

65. VLSI Design & Implementation of UART Asynchronous Transmitter/Receiver using FPGA with Verilog/VHDL code

66. VLSI Design & Implementation of RS-232 Transmitter/Receiver using FPGA with Verilog/VHDL code

67. VLSI Design & Implementation of Asynchronous Serial controller using FPGA with Verilog/VHDL code

68. VLSI Design & Implementation of Universal Serial Bus USB Device Controller using FPGA with Verilog/VHDL code

69. VLSI Design & Implementation of GPS-GSM based Home Automation System using FPGA with Verilog/VHDL code

70. VLSI Design & Implementation of 16/32/64-bit Low Power RISC/CISC Processor using FPGA with Verilog/VHDL code

71. VLSI Design & Implementation of Multichannel I2S Audio Controller using FPGA with Verilog/VHDL code

72. VLSI Design & Implementation of Asynchronous FIFO using FPGA with Verilog/VHDL code

73. VLSI Design & Implementation of AHB Master/Slave using FPGA with Verilog/VHDL code

74. VLSI Design & Implementation of AMBA AHB to PVCI Bridge using FPGA with Verilog/VHDL code

75. VLSI Design & Implementation of Huffman Encoder/Decoder using FPGA with Verilog/VHDL code

76. VLSI Design & Implementation of Programmable 16-Tap FIR Filter using FPGA with Verilog/VHDL code

77. VLSI Design & Implementation of 2-D Convolution Engine using FPGA with Verilog/VHDL code

78. VLSI Design & Implementation of VGA/LCD Controller using FPGA with Verilog/VHDL code

79. VLSI Design & Implementation of JTAG TAP controller using FPGA with Verilog/VHDL code

80. VLSI Design & Implementation of Booth Multiplier using FPGA with Verilog/VHDL code

81. VLSI Design & Implementation of Pipeline JPEG Encoder using FPGA with Verilog/VHDL code

82. VLSI Design & Implementation of Cyclic Redundancy Check ECRC/LCRC Error Check using FPGA with Verilog/VHDL code

83. VLSI Design & Implementation of Vehicle Tracking & Safety System using FPGA with Verilog/VHDL code

84. VLSI Design & Implementation of Low Power FIR Filter using FPGA with Verilog/VHDL code

85. VLSI Design & Implementation of Pattern Generator using FPGA with Verilog/VHDL code

86. VLSI Design & Implementation of PCI Express using FPGA with Verilog/VHDL code

87. VLSI Design & Implementation of Highspeed USB 2.0/Superspeed USB 3.0 Transmitter and Receiver using FPGA with Verilog/VHDL code

88. VLSI Design & Implementation of Wishbone Controller using FPGA with Verilog/VHDL code

89. VLSI Design & Implementation of PVCI Master/Slave using FPGA with Verilog/VHDL code

Get free daily email updates!

Follow us!