Are there any VHDL source code libraries available to save me having to re-invent common code fragments and functions?

There are a few libraries available for most levels of VHDL design. The IEEE library contains very low-level type-and-function packages. The std_logic_1164 package is an industry standard, and practically every piece of VHDL you ever write will use this package; the types std_logic and std_logic_vector are the overwhelmingly dominant types for anything related to digital design. For arithmetic, numeric_std (from the same IEEE library) is a collection of functions that work on std_logic and its derivatives. For other libraries of components, have a look in the comp.lang.vhdl FAQ.

I've heard that VHDL is very inefficient for FPGAs. Is that true?

It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.

I can see how to write abstract behavioural descriptions in VHDL, but how do you describe and simulate the actual hardware?

This is probably the biggest hurdle that many hardware engineers face when moving to VHDL. After all, sometimes we need to be able to describe actual implementation as well as abstract functionality. The way to describe "physical" hardware in VHDL is to write VHDL models of those components. This is supported in VHDL through the use of instantiation. VHDL does not allow you to physically simulate your hardware. You can only simulate a model of that component in a VHDL simulation.

Historically, gate-level simulation using VHDL has been notoriously slow. This led to the creation of the 1076.4 working group to provide a mechanism to allow faster gate-level simulation using VHDL. Their effort became known as the VITAL standard. VITAL is not a VHDL issue for you, but an EDA vendor/ASIC supplier issue. A simulator is VITAL compliant if it implements the VITAL package in its kernel (this is faster than simulating the VITAL primitives in the VITAL package). You don't need to change your VHDL netlist; your ASIC vendor needs to have a VITAL compliant library though, in order for you to take advantage of the simulation speed up. Thus the ASIC vendor's library elements need to be implemented entirely in VITAL primitives. Note that many companies use Verilog for gate-level simulations as it is still faster than VHDL, even with the improvements from VITAL. The reason is that Verilog was designed from the start as a gate-level simulation language.

Can you give me a measure of the productivity improvements I should expect from VHDL?

Well, do you believe the hype! Yes, ultimately there are considerable productivity gains to be had from using high-level design techniques in conjunction with synthesis technology, providing that your designs are: complex, amenable to synthesis, not dependent upon the benefits of a particular technology.

Obviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let's face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into HLD. Of course, once you are benefiting from HLD productivity gains, the specification phase becomes more significant. OK, that's HLD: VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process. However, you won't get those benefits immediately. Your first VHDL-based project will probably take slightly longer than if you had used your previous design process.

Are there any tools to generate VHDL test benches automatically?

The basic answer is no. Writing a testbench can be a complex task, and can be more complex than the design being tested. If you mean "Can I get a code framework for a simple testbench", then a number of tools provide simple "testbench templates"; even the Emacs editor VHDL mode can do this! For more advanced ways of writing testbenches, you might want to look at the so-called "Testbench Automation" tools, such as SystemVerilog, SystemC Verification Library, Cadence Specman, and Synopys Vera. These tools involve learning another language of course. If you want to know how to write more complex testbenches (for instance to cope with data arriving in a different order from the order it entered a device).

A VHDL design can be moved to any tool or technology. Right?

On the face of it, this is true. VHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may have broad agreement of what constitutes synthesizable code, but may interpret that code in different ways.

Is VHDL going to be developed further?

You might have heard a lot about System Verilog, and wondered if VHDL is going to also be developed? There is an activity to develop an improved VHDL, and VHDL-2008 was released in January 2009. This might help engineers to write efficient code in VHDL.