It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.
Subscribe to:
Post Comments (Atom)
-
This is in continuation of our previous post on Low Power Design Techniques , where we learned about different types of strategies used to... -
Formal Definition An interface constant declared in the block header of a block statement, a component declaration, or an entity declaratio...
-
Formal Definition Simulation control tasks allow you to stop or quit simulation. Simplified Syntax $ stop [(n)] ; $finish [(n)] ; Descri...
-
From online payments and electronic banking transactions to organizing company documents and mission-critical supply chain management system...
-
Below code gives basic structure of a verilog module module M (P1, P2, P3, P4); input P1, P2; output [7:0] P3; inout P4; reg [7:0] R1, M1...
No comments:
Post a Comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.