It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.
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Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible comp...
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There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “...
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This is in continuation of our previous post on Low Power Design Techniques , where we learned about different types of strategies used to...
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The FP Adder is a single-precision, IEEE-754 compliant, signed adder/substractor. It includes both single-cycle and 6-stage pipelined design...
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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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