It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.
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Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible comp...
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Counters are generally made up of flip-flops and logic gates. Like flip-flops, counters can retain an output state after the input condition...
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Very often we come across questions from VLSI engineers that "Which scripting language should a VLSI engineer should learn?". Well...
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In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting. A timing problem might require that a high...
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Formal Definition A procedure is a subprogram that defines algorithm for computing values or exhibiting behavior. Procedure call is a state...
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