Draw AND gate using 2x1 MULTIPLEXER

Look at the truth table of AND gate. When any of the one input is zero output is always zero (or same as that input); when the other input is one, output is dependent on the other input and is same as the other input. Using this property we can draw AND gate in four different ways using 2:1 MUX as shown in the above figure.

Similar concept can be applied to create all basic gates from 2:1 MUX. I will publish all these in coming blog posts along with the elaborated

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Glimpse to Intel’s 3rd Generation Core Ivy Bridge Processors

World’s First 22nm Quad-Core Processors Bring Up to Twice the Visual Performance for Unmatched Overall PC Experiences

HIGHLIGHTS

• Quad-core processors available starting today in powerful, high-end desktop, laptop, and sleek and beautiful all-in-one designs.
• Accelerates Intel’s “Tick-Tock” cadence for first time to simultaneously bring to market the world’s first processors developed on 22nm manufacturing process using innovative 3-D tri-gate transistor technology and a new graphics architecture.
• Up to twice the HD media and 3-D graphics performance, as well as significant processor performance, deliver stunning visual experiences from mainstream gaming to HD video editing.
• Ultrabook™ devices, all-in-one (AIO) platforms, business PCs and Intelligent systems in retail, healthcare and other industries will benefit from Intel’s newest processors, with formal announcements in the coming months.

Intel Corporation today introduced the quad-core 3rd generation Intel® Core™ processor family, delivering dramatic visual and performance computing gains for gamers, media enthusiasts and mainstream users alike. Available now in powerful, high-end desktop, laptop and sleek all-in-one (AIO) designs, the new processors are the first chips in the world made using Intel’s 22-nanometer (nm) 3-D tri-Gate transistor technology.

The combination of Intel’s cutting-edge 3-D tri-gate transistor technology and architectural enhancements help make possible up to double the 3-D graphics and HD media processing performance compared with Intel’s previous generation of chips. As a result of the stunning, built-in visual performance, all the things people love to do on their PCs — from creating and editing videos and photos, surfing the Web, watching HD movies or playing mainstream games — are quicker, crisper and more life-like. With as much as 20 percent microprocessor performance improvements and new technologies to speed the flow of data to and from the chips, the new processors further extend Intel’s overall performance leadership.

In the coming months, additional versions of the 3rd generation Intel Core processors will be available to power a new wave of systems ranging from Ultrabook™ devices, to servers and intelligent systems in retail, healthcare and other industries.

"The 3^rd generation Intel Core processors were created from the ground up to generate exciting new experiences," said Kirk Skaugen, Intel vice president and general manager of the PC Client Group. "Our engineers have exceeded our expectations by doubling the performance of media and graphics versus the best processors we’ve built until today, which means incredible new visual experiences are here for new all-in-one PCs and upcoming Ultrabook devices. What makes all this possible is the combination of Intel’s leading manufacturing and processor architecture, and our unwavering commitment to drive computing innovations forward."

“Tick-Plus” – The Intel Advantage
The performance gains found in the new processors are due in part to the groundbreaking, three-dimensional structure of the new Intel transistors. Until today, computers, servers and other devices have used only two-dimensional planar transistors. Adding a third dimension to transistors allows Intel to increase transistor density and put more capabilities into every square millimeter of these new processors. Intel has once again re-invented the transistor and delivered an unprecedented combination of performance and energy efficiency, thus sustaining the pace of technology advancement and fueling Moore’s Law for years to come.

Intel engineers also reworked the graphics architecture of the 3rd generation Intel Core processors, helping to deliver dramatic improvements in the overall visual experience. Changing the chips’ architecture while at the same time shrinking the size of the underlying transistors is an acceleration of Intel’s “tick-tock” model. Previously, the company adhered to a strict “tick-tock” model in which a new manufacturing process was introduced in 1 year (the “tick”), and the architecture of the chip (the “tock”) was altered the next. The ability to accelerate the roadmap and change both the chips’ architecture and the manufacturing process at the same time was made possible because Intel is one of the few companies that both designs and manufactures its chips, a method called Integrated Device Manufacturing.

Get Visual and Get Your Game On
The 3rd generation Intel® Core™ processor with Intel® HD Graphics 4000 delivers up to two times better 3-D graphics performance compared to the previous-generation processor, bringing more gaming fun with richer detail at higher resolutions. Intel HD Graphics 4000 supports Microsoft* DirectX 11, OpenGL 3.1 and OpenCL 1.1.

“The 3-D graphics capabilities in 3rd generation Intel Core processors represent a major step forward for PC gaming,” said Gabe Newell, co-founder and managing director of Valve Software, a leading online game provider. “Mainstream gamers are going to have a blast playing titles like our upcoming DOTA 2 on Intel HD Graphics 4000.”

Great visual experience is about more than just gaming. Online video continues to grow dramatically, and is expected to comprise half of all Internet traffic this year.** The key to making video fun is the ability to quickly convert it for online sharing with friends and family. With Intel^® Quick Sync Video 2.0 technology built into the new processors, people can convert their videos up to two times faster than even last year’s processors and up to 23 times faster than PCs just three years old.

Experiences, Secured. Platform, Enhanced.
The 3rd generation Intel Core processor also adds security features, including Intel^® Secure Key and Intel® OS Guard to safeguard personal data and identity. Intel Secure Key consists of a digital random number generator that creates truly random numbers to strengthen encryption algorithms. Intel OS Guard helps defend against privilege escalation attacks where a hacker remotely takes over another person's system. These two features join existing platform security features such as Intel^® Identity Protection Technology (Intel® IPT) and Intel^® Anti-Theft technology (Intel® AT) to help make Intel platforms some of the most secure in the industry. When paired with the Intel^® Series 7 Chipset, the new processors with Intel IPT can make a portion of the screen unreadable to spyware with the “protected transaction display” feature, helping prevent a hacker from obtaining login credentials that could lead to identity theft.

Platforms based on 3^rd generation Intel Core processors also deliver faster data transfer capabilities made possible by USB 3.0 integrated into the Series 7 Platform Controller Hub (PCH) and PCI Express 3.0 integrated into the processor. These next-generation I/O technologies bring bigger data pipes to the platform to keep data moving, minimizing any interruption to the PC experience.

Processor and System Availability
Systems based on quad-core 3rd generation Intel Core processor products will be available beginning this month from leading system makers. Boxed versions of these processors will also be available this month from online, retail and channel resellers. Additional versions of the 3^rd generation Intel Core processor products for servers, intelligent systems in retail, healthcare and other industries, Ultrabook devices and laptops and more will be available later this year.

 

Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium

Just published is the press release and tip-sheet on the 2012 VLSI Symposia on VLSI Technology and Circuits, this year in Hawaii. Listed first in the VLSI Technology highlight papers is Intel’s paper, “A 22nm High-Performance and Low-Power CMOS Technology Featuring Fully Depleted Tri-Gate Transistors, Self-Aligned Contacts and High-Density MIM Capacitors”, to be presented by Chris Auth in slot T15-2.

There was a fair bit of frustration at last year’s IEDM that there was no Intel paper on their tri-gate technology, although they had several others at the conference. The Intel folks I talked to said that there was reluctance to publish, since the other leading-edge semiconductor companies were not presenting – conferences were no longer the exchange of information that they have been in the past. I have to say I agree, some companies are keeping their technological cards very close to their corporate chests these days!

Also, no product was in the public domain at that point, though Intel claimed to be in production. By the time VLSI comes around in June, we should all be able to get Ivy Bridge based Ultrabooks, and we at Chipworks will have pulled a few chips apart.

In the paper the process is claimed to have “feature sizes as small as eight nm, third-generation high-k/metal gate stack technology, and the latest strained-silicon techniques. It achieves the highest drive currents yet reported for NMOS and PMOS devices in volume manufacturing for given off-currents and voltage. To demonstrate the technology’s versatility and performance, Intel researchers used it to build a 380-Mb SRAM memory using three different cell designs: a high-density 0.092- µm2 cell, a low-voltage 0.108- µm2 cell, and a high-performance 0.130-µm2 cell. The SRAM operated at 4.6 GHz at 1 V.”

The tip-sheet also posted the first Intel tri-gate images that I’ve seen in a while:

TEM images of Intel 22-nm PMOS tri-gate transistor (a) and source/drain region (b)

Here we are looking at sections parallel to the gate, across the fin. There is no scale bar, so fin width is an unknown; and the taper on the fin is a bit of a surprise. The top of the fin is rounded, likely to avoid reliability problems from electric field concentration at corners.

In the gate metal, there seems to be a layer of titanium nitride (TiN) above the thin dark line that is the high-k, so we can surmise that the PMOS work-function metal is TiN, as in previous generations. The gate fill itself is very black, so that appears to have been changed from the Al/Ti fill used before; possibly to tungsten or some other heavier metal.

The source/drain image confirms the use of epi, and the darker area is again likely SiGe, both for strain and resistance improvement. At the moment it’s hard to say if the taper is a function of manufacturing convenience (easier to etch?), or if there are some device physics advantages that improve transistor operation. We’ll see in June!

Xilinx Inaugurates Expanded Site in Hyderabad for R&D, Technical Support

Xilinx India team pivotal to development, delivery & support of company's flagship programmable platforms.

 

Xilinx, Inc. underscored its commitment to the emerging, high-growth market and its growing employee base in India with the inauguration of a new, expanded Xilinx India site in Hi-Tech city. The 131,000 square-foot office building is more than double the size of the previous site to accommodate engineering labs and collaboration space for end-to-end product development, a larger, energy-efficient data center, and expanded facilities for customer and employee events.

Hosted by Xilinx President and CEO, Moshe Gavrielov, Senior Vice President of Programmable Platforms Development, Victor Peng, and Xilinx India Site Director and CTO, Vamsi Boppana, the inaugural event began with a traditional lamplighting ceremony to mark the beginning of an exciting new chapter for Xilinx India.

The Xilinx India site, which represents the largest R&D centre outside of the company's U.S. headquarters, is a critical contributor to Xilinx's success as the world's leading provider of 'all programmable' technologies and devices. This includes its newest, industry leading portfolio of 28nm 7 series and Zynq(TM)-7000 Extensible Processing Platform (EPP) families, which enable breakthroughs in price/performance/watt and programmable systems integration.

Currently, more than 400 employees in Hyderabad report into Xilinx's Programmable Platforms Development (PPD) and Worldwide Technical Support groups, which are global organizations responsible for development and delivery of the company's flagship programmable platforms and support of local, regional and multi-national customers in India. The expansion and increasing role of the Xilinx India engineering team is well aligned to the National Policy on Electronics goals to transform India into a global R&D hub.

"We're proud to commemorate the opening of our new Hyderabad site today and to celebrate the incredible contributions of our employees in India," said Gavrielov at today's inauguration ceremonies. "The Xilinx India engineering team will continue to play a pivotal role in our success as part of Xilinx's world-class PPD engineering organization. Notably, more than half the Zynq engineering team is based in India, with some aspects entirely designed and verified in India. The India team has sole ownership and development responsibility for significant aspects of our next-generationtool suite accelerating programmable design productivity."

Reset synchronizer

A day before there was a discussion about Synchronous and Asynchronous reset and Reset Synchronizer. I would like to share my views and some Ideas that I came to know.

Implementation of Synchronous and Asynchronous reset should depend on what you are looking at. There is a timing constraint on the rising edge of the reset ( assuming an active low reset) which can create one cycle uncertainty in the data being latched in by the FF. So for example if the start of a state machine depends on when the input FF gets the data and it doesn't matter if it starts one cycle early or late, there is no problem in using Asynchronous Reset. But if you have a high speed interface with say 6 bits of data being latched by the FF's and reset release happens very close to the clock edge then you have a serious problem that some Flops can get the data and some won't.

So it is really depended on what your design does on what kind of reset you should have. The safe methodology from my point of view is to use Asynch resets as long as the clock starts after the reset has been released.  Or to synchronize the Reset with the clock and make sure that the reset network delay including the CLK->Q delay of the synchronizing flop is less then the clock period - the worst removal timing of the FF's on the network.

 

VHDL Attributes

Formal Definition
A value, function, type, range, signal, or constant that may be associated with one or more named entities in a description.

Simplified Syntax
object'attribute_name

Description
Attributes allow retrieving information about named entities: types, objects, subprograms etc. VHDL standard defines a set of predefined attributes. Additionally, users can define new attributes, and then assign them to named entities by specifying the entity and the attribute values for it. See attributes (user-defined) for details.

Predefined attributes denote values, functions, types, and ranges that characterize various VHDL entities. Separate sets of attributes are predefined for types, array objects or their aliases, signals and named entities.

Each type or subtype T has a basic attribute called T'Base, which indicates the base type for type T (Table 1). It should be noted that this attribute could be used only as a prefix for other attributes.

Table 1. Attributes available for all types

Attribute	Result
T'Base	base type of T

Scalar types have attributes, which are described in the Table 2. Letter T indicates the scalar type.

Table 2. Scalar type attributes

Attribute	Result type	Result
T'Left	same as T	leftmost value of T
T'Right	same as T	rightmost value of T
T'Low	same as T	least value in T
T'High	same as T	greatest value in T
T'Ascending	boolean	true if T is an ascending range, false otherwise
T'Image(x)	string	a textual representation of the value x of type T
T'Value(s)	base type of T	value in T represented by the string s

Discrete or physical types and subtypes additionally have attributes, which are described in Table 3. The discrete or physical types are marked with letter T before their names.

Table 3. Attributes of discrete or physical types and subtypes

Attribute	Result type	Result
T'Pos(s)	universal integer	position number of s in T
T'Val(x)	base type of T	value at position x in T (x is integer)
T'Succ(s)	base type of T	value at position one greater than s in T
T'Pred(s)	base type of T	value at position one less than s in T
T'Leftof(s)	base type of T	value at position one to the left of s in T
T'Rightof(s)	base type of T	value at position one to the right of s in T

Array types or objects of the array types have attributes, which are listed in the Table .4. Aliases of the array type objects have the same attributes. Letter A denotes the array type or array objects below.

Table 4. Attributes of the array type or objects of the array type

Attribute	Result
A'Left(n)	leftmost value in index range of dimension n
A'Right(n)	rightmost value in index range of dimension n
A'Low(n)	lower bound of index range of dimension n
A'High(n)	upper bound of index range of dimension n
A'Range(n)	index range of dimension n
A'Reverse_range(n)	reversed index range of dimension n
A'Length (n)	number of values in the n-th index range
A'Ascending(n)	True if index range of dimension n is ascending, False otherwise

Signal attributes are listed in Table 5. Letter S indicates the signal names.

Table 5. Signals attributes

Attribute	Result
S'Delayed(t)	implicit signal, equivalent to signal S, but delayed t units of time
S'Stable(t)	implicit signal that has the value True when no event has occurred on S for t time units, False otherwise
S'Quiet(t)	implicit signal that has the value True when no transaction has occurred on S for t time units, False otherwise
S'Transaction	implicit signal of type Bit whose value is changed in each simulation cycle in which a transaction occurs on S (signal S becomes active)
S'Event	True if an event has occurred on S in the current simulation cycle, False otherwise
S'Active	True if a transaction has occurred on S in the current simulation cycle, False otherwise
S'Last_event	the amount of time since last event occurred on S, if no event has yet occurred it returns Time'High
S'Last_active	the amount of time since last transaction occurred on S, if no event has yet occurred it returns Time'High
S'Last_value	the previous value of S before last event occurred on it
S'Driving	True if the process is driving S or every element of a composite S, or False if the current value of the driver for S or any element of S in the process is determined by the null transaction
S'Driving_value	the current value of the driver for S in the process containing the assignment statement to S

The named entities have attributes described in Table 6. Letter E denotes the named entities.

Table 6. Attributes of named entities

Attribute	Result
E'Simple_name	a string representing the simple name, character literal or operator symbol defined in the declaration of the item E
E'Path_name	a string describing the path through the design hierarchy, from the root entity or package to the item E
E'Instance_name	a string describing the path through the design hierarchy, from the root entity or package to the item E, but including the names of the entity and architecture bound to each component instance in the path

Paths which can be written using E'Path_name and E'Instance_name are used for reporting and assertion statements. They allow specifying precisely where warnings or errors are generated. E'Simple_name attribute refers to all named entities, E'Path_name and E'Instance_name can refer to all named entities apart from the local ports and generic parameters in the component declaration.

There is one more predefined attribute: 'Foreign' that allows the user to transfer additional information to the simulator. The information contains the instruction for special treatment of a given named entity. The exact interpretation of this attribute, however, depends on its implementation in particular simulator.

 

Examples

Example 1

type Table is array (1 to 8) of Bit;
variable Array_1 : Table := "10001111";
Array_1'Left, the leftmost value in index range of Table array, is equal to 1.

Example 2

type Table is array (Positive range <>) of Bit;
subtype Table_New is Table (1 to 4);
Table_New'Base, the base type of the Table_New subtype is Table.

Example 3

type New_Range is range 1 to 10;
New_Range'Ascending is TRUE (the New_Range type is of ascending range).

Example 4

type New_Values is (Low, High, Middle);
New_Values'Pred(High) will bring the 'Low' value.

Example 5

type Table is array (1 to 8) of Bit;

Table'Range(1) is the range of the first index of Table type and returns '1 to 8'; Table'Range will have the same interpretation for one dimensional array.

 

Important Notes

• Not all predefined attributes are supported by synthesis tools; most tools support 'high, 'low, 'left, 'right, range, 'reverse_range, 'length and 'event. Some also support'last_value and 'stable.

VHDL Configuration

Used to bind component instances to design entities and collect architectures to make, typically, a simulatable test bench. One configuration could create a functional simulation while another configuration could create the complete detailed logic design. With an appropriate test bench the results of the two configurations can be compared.

Note that significant nesting depth can occur on hierarchal designs. There is a capability to bind various architectures with instances of components in the hierarchy. To avoid nesting depth use a configuration for each architecture level and a configuration of configurations. Most VHDL compilation/simulation systems allow the top level configuration name to be elaborated and simulated.

Syntax:
configuration identifier of entity_name is
     [ declarations , see allowed list below ]
     [ block configuration , see allowed list below ]
  end configuration identifier ; 

To understand configuration in depth let us consider below entity and architectures,

Entity E1 is
end E1;

Architecture A1 of E1 is
end Architecture A1;

Architecture A2 of E1 is
end Architecture A2;

Architecture A3 of E1 is
end Architecture A3;

Entity E2 is
end E2;

Architecture A1 of E2 is
   Component E1;
begin
   L1: E1 port map ();
   L2: E1 port map ();
end Architecture A1;

Architecture A2 of E2 is
begin
behavioural discription;
end Architecture A2;

Entity E3 is
end E3;

Architecture A1 of E3 is
   Component E1;
   Component E2;
begin
   L1: E1 port map ();
   L2: E2 port map ();
   L3: E2 port map ();
   L4: E1 port map ();
end Architecture A1;

Architecture A2 of E3 is
begin
behavioural discription;
end Architecture A2;

Below is the detailed configuration for entity E3;

Configuration C1 of E3 is
   for A1
        for L1 : E1
        use entity work.E1(A1);
        end for;

        for L2 : E2
        use entity work.E2(A2);
        end for;

        for L3 : E2
        use entity work.E2(A1);
             for A1
             use entity work.E1(A2);
             end for;
        end for;

        for L4 : E1
        use entity work.E1(A3);
        end for;
   end for;

end Configuration C1;