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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Saturday, 11 January 2014

Modelsim Tips and Tricks

1. How to get rid of Std Arithmetic warnings around 0 ns?

    # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
    #    Time: 0 ns  Iteration: 1  Instance: /cordic_tb/uut/add3

    Simply turn the Std checking off in your  .do or .tcl script file, example:

    set StdArithNoWarnings 1
    run 0 ns;
    set StdArithNoWarnings 0
    # Continue script

2. How to get rid of Std Arithmetic warnings until my reset is asserted?

    If the warnings continue until a certain time or when a signal is asserted then the when statement can help out.

    Example: the Std warnings can be ignored until the signal reset_s is asserted

    when -label enable_StdWarn {reset_s == '1'} {echo "Enable StdArithWarnings" ; set StdArithNoWarnings 0 ;}

    Example: the Std warnings can be ignored until 3800 ns

    when -label enable_StdWarn {$now == @3800 ns} {echo "Enable StdArithWarnings" ; set StdArithNoWarnings 0 ;}

3. How to stop the simulator without using asserts?

    The usual way to stop the simulator is to use the assert statement in VHDL. However, not everybody likes the Failure/Error message in the transcript window.

    # ** Failure: End of Simulation
    #    Time: 360 ns  Iteration: 0  Process: /test_tb/line__35 File: test_tb.vhd

    An easy solution is the same construct as shown above. Simple add a signal to your testbench and assert this signal at the end of the simulation. Then use the when statement in your script to stop the simulator.

    Example: stop the simulator when the signal end_of_simulation='1'

    when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation" ; stop ;}

    # End of simulation
    # Simulation stop requested

    Note: for maximum portability to other simulators the assert statement is recommended method!

4. How to speed up simulation/reduce wlf file size?

    There are many ways to speed up simulation. If you are performing long simulation you can speed up the simulation by turning off the signal logging to the wlf file until you reach the time of interest.

    Example: Disable signal logging until time 4420 us

    nolog -all
    when -label start_logging {$now == @4420 us} {echo "Start logging " ; log -r *;}

Tip: how to find out what a ModelSim error message means

    Error messages and exit codes are described in the User's Manual, however a quick way to get this information is to use the verror command. Simply type verror #error_number to get a detailed description on the error number.


Related Posts:

1. Customize the ModelSim Wave View in the Xilinx ISE Simulation
2. Compiling Xilinx library for ModelSim simulator

Friday, 3 January 2014

India's fab project fails to attract big chip players

FAB-INDIA-IBM-ST Two consortia, led by Hindustan Semiconductor Manufacturing Corp. and Jaypee Associates, remain the top contenders to construct and equip proposed wafer fabrication facilities in India. No large semiconductors manufacturers have emerged as leaders for the project. HSMC is working with STMicroelectronics and Silterra, while Jaypee is collaborating with IBM Microelectronics and Tower Semiconductor.

Under the current proposals, Jaypee has tied up with IBM and Tower Jazz and has proposed a facility in Greater Noida with an investment of Rs 26,300 crore, while HSMC has partnered with ST Microelectronics and Silterra and has planned its unit at Prantij near Gandhinagar in Gujarat with an investment of Rs 25,250 crore.

India is trying to create an electronics manufacturing ecosystem to prevent the loss of billions of dollars of foreign exchange in such imports every year. This bill, expected to reach $55 billion (aboutRs 3.4 lakh crore) by 2020 from about $7 billion (Rs 43,600 crore) now, is projected to outstrip oil imports, according to a report commissioned by the industry lobby India Electronics and Semiconductor Association last year.

According to two government officials, the Department of Electronics and Information Technology (DeitY) has received only two new proposals - one by Interactivity Group (supported by a group of IIT alumni) and another by APSTL, an Arizona-headquartered technology firm. Even though an empowered committee set up to evaluate all the proposals is still studying them, an official said it is unlikely something concrete will come out of the two new applications.

With the government's support for setting up the fab firming up at about 40 per cent of the total cost, officials were keen on figuring out if other chipmakers could also be enticed to show interest.

Typically, setting up a chip foundry costs around $4-5 billion (Rs 24,800-31,000 crore). "The idea was, with the incentives firmed up, could we push the fence-sitters off the fence, but that didn't happen," the industry executive said. The deadline to submit initial plans in the fab under a separate call for expressions of interest ran out in November, and there have been no new viable plans submitted other than the two the government had already approved in-principle.

However, a lack of interest the second time around as well underlines the concerns about the feasibility of setting up fab units in the country. Experts argue the long-gestation period and the technology mandates of the government may diminish the usefulness of the projects when they finally come up. The facilities are expected to start production only sometime in 2017.

Tuesday, 31 December 2013

Run-time configurations in OVM

Overriding or changing the existing configuration of VE components from testcases/sequences is something needed every now and then while working in system verilog based environment.  Also in many circumstances we need to share some variables/flags between multiple components of env(ovm_env) not necessarily through the TLMs.

Some of the examples are like,

· Enabling/disabling specific streams of scoreboard.

· Enabling/disabling specific checkers after specific sequences are executed.

· Informing driver/sequencer to inject error into some Nth packet  etc...

Let’s see and understand how this could be achieved in OVM based system-verilog environment. OVM’s configuration table and its methods provide easy way to achieve this.

Let’s assume that one needs to disable the specific stream of scoreboard using OVM’s configuration table from testcases.

Step 1: Define a configuration class containing all the parameters/configuration fields which need to be changed run-time,

class xyz_config extends ovm_object;

  bit sb_stream_disable;

  `ovm_object_utils_begin(xyz_config)

    `ovm_field_int(sb_stream_disable, OVM_ALL_ON)

  `ovm_object_utils_end

  //Constructor

  ….

endclass : xyz_config

Based on the complexity of the environment you can also create multiple configuration classes to configure specific agents or specific set of components.

Step 2: Use the configuration class in scoreboard to disable the applicable data-stream.

class xyz_scoreboard extends ovm_scoreboard;

  xyz_config cfg;

  `ovm_component_utils_begin(xyz_scoreboard)

    `ovm_object_utils(cfg, OVM_ALL_ON)

  `ovm_component_utils_end

  //Constructor

  //Run thread

  task run();

  //Use the cfg.disable_sb_stream to disable the scoreboard data stream

  ....

  endtask : run

endclass : xyz_scoreboard

As it is specified here, `ovm_object_utils is must here. It 'gets' the configuration instance from the OVM’s configuration table for ‘this` class.

Step 3: From the OVM based testcases disable the scoreboard at required point of time in the simulation.

class test extends ovm_test;

  xyz_cfg cfg = new();

  function void build();

    super.build();

    //Sharing the config. instance at target path.

    set_config_obect(“env.scoreboard”,”cfg”,cfg,,0);

  endfunction : build

  task run();

    //Some test code

    //After some time disable the scoreboard stream

    cfg.disable_sb_stream = 1;

   //Other code

  endtask : run

endclass : test

As you can see, one needs to ‘new’ the config. instance and share it with required classes using set_config_object method of ovm. The usage of set_config_object function with proper arguments is one of the crucial point here.
Let’s understand what arguments should be passed to this function,

1st argument is a string which specifies the target path where configuration needs to be shared. One could also use wildcard expressions here as env.*

2nd argument specifies the string-instance name of the object.

3rd argument is the object handle.

4th argument specifies whether object needs to be cloned before passing it to targeted component. For run-time passing set it to 0. This means all the components in env. which attempt to get the "cfg" from configuration table will use the same object throughout the simulation.

In cases where you have only few fields to share, you can also use OVM’sset_field_int and get_field_int methods.

The only additional step needed to pass the config. runtime is to call theapply_config_settings() method on the targeted component, as explained inthis thread under OVM forum.

Enjoy Configuring!!

Thursday, 12 December 2013

Broadcom releases satellite-constellation location IC

8521338394_ec9d0e1f06_c Broadcom Corporation has introduced a Global Navigation Satellite System (GNSS) chip, designated BCM47531, that generates positioning data from five satellite constellations simultaneously (GPS, GLONASS, QZSS, SBAS and BeiDou), totaling 88 satellites. The newly added Chinese BeiDou constellation increases the number of satellites available to a smartphone, enhancing navigation accuracy, particularly in urban settings where buildings and obstructions can cause interference.

The company’s new GNSS SoC is based on its widely deployed architecture that reduces the “time to first fix” (TTFF) and allows smartphones to quickly establish location and rapidly deliver mapping data. The SoC also features a tri-band tuner that enables smartphones to receive signals from all major navigation bands (GPS, GLONASS, QZSS, SBAS, and BeiDou) simultaneously.

The BCM47531 platform is available with Broadcom’s Location Based Services (LBS) technology that delivers satellite assistance data to the device and provides an initial fix time within seconds, instead of the minutes that may be required to receive orbit data from the satellites themselves.

The BCM47531 brings a number of powerful features to the table:

  • Simultaneous support of five constellations (GPS, GLONASS, QZSS,SBAS and BeiDou) allows for position calculations based on measurements from any of 88 satellites.
  • Broadcom's tri-band tuner brings the ability to receive all navigation bands, GPS (which includes QZSS and SBAS), GLONASS and BeiDou simultaneously to the commercial GNSS market without having to reconfigure and hop between bands.
  • Utilizes BeiDou signals for up to 2x improved positioning accuracy.
  • Best-in-class Assisted GNSS (AGNSS) data available worldwide from Broadcom's hosted reference network.
  • Allows a device to interchangeably use the best signal from any satellite regardless of the constellation, ensuring better accuracy in urban and mountainous environments.
  • Features advanced digital signal processing for interference rejection that enables satellite signal search and tracking during LTE transmission.
  • Leverages Broadcom's connectivity solutions including Wi-Fi, Bluetooth Smart, Near Field Communications (NFC), Instant Messaging System (IMES) and handset inertial sensor data for best indoor/outdoor location.

Nanobubbles with graphene - diamond substrate

Observing HighPressure Chemistry in Graphene Bubbles<br /> Scientists at the National University of Singapore have come up with a way to trap liquids inside nanoscale bubbles made of graphene, topping a diamond substrate. "We discovered a way to bond the two materials together by heating the diamond to its reconstruction temperature where its surface hydrogen is desorbed," said Kian Ping Loh, the research team leader.

The team were able to use these graphene bubbles as high pressure chemical reactors to perform reactions that are normally forbidden, such as fullerene polymerisation.

Anvil cells generate extremes of pressure by applying a force over as small an area as possible. As one of the thinnest elastic membranes in existence, graphene can be strain-engineered to form nanometre bubbles; spaces small enough to reach extremes of pressure when heated.2 Thanks to the bubbles’ impermeability to almost any fluid, this implies that graphene could be used to seal and pressurise fluids in nano-sized liquid cells.

Read more >>

Saturday, 28 September 2013

China used more than half of world's ICs in 2012

0023ae82ca0f13af1f6d03 China's semiconductor use has hit a record high and accounts for more than half of the global market, but the country is overly dependent on foreign suppliers for relevant products, according to a PricewaterhouseCoopers report issued on Thursday.

With an 8.7 percent growth in 2012, China's semiconductor use was 52.5 percent of the total worldwide, said a PwC report titled China's Impact on the Semiconductor Industry - 2013 Update. Semiconductors act as an engine now driving an increasing amount of the technology in people's lives.

The growth in Chinese semiconductor use is a remarkable contrast to the global market for semiconductors, which experienced an overall decline of3 percent in 2012, the report said.

China is expected to continue its domination of semiconductor purchasing in the foreseeable future with its market share possibly reaching 60 percent by 2017,Raman Chitkara, PwC's global technology and semiconductor leader, said in an interview with China Daily.

"One of the major reasons why China has grown so big in semiconductor consumption is that the country isrising to become the world's capital of electronic manufacturing," Chitkara said.

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Sunday, 15 September 2013

India Plans To Build 2 Wafer Fabs

FAB_INDIA The government of India on Thursday approved "in principle" a plan to construct and equip two wafer fabrication facilities in the country, in a move designed to reduce India's reliance on imported semiconductors. Two consortia will go ahead with the twin fab projects. One is led by STMicroelectronics, an integrated device manufacturer, and the other is spearheaded by Tower Semiconductor, a silicon foundry. These companies will add their names to list of VLSI companies in India and boost the manufacturing capability.
"The Cabinet has given in-principle approval for setting up of semiconductor wafer fabrication manufacturing facilities," Information and Broadcasting Minister Manish Tewari told reporters after a meeting of the Union Cabinet, chaired by Prime Minister Manmohan Singh.
After considering proposals from two consortia, the government took the decision. The government received proposals from two consortiums to set up chip fabrication units in the country. One was led by Israel's Tower Jazz and the other was led by Geneva–based chipmaker STMicroelectronics.
Israel-based foundry chipmaker Tower Semiconductor Ltd, which operates under the brand name TowerJazz, partnered with IBM and Indian infrastructure conglomerate Jaypee Associates to build and operate a 300mm chip facility in India. On the other hand, STMicroelectronics partnered with Hindustan Semiconductor Manufacturing Corp. (HSMC).
Welcoming the government's decision, India Electronics & Semiconductor Association (IESA) President PVG Menon said, "The IESA deems the fab a highly strategic game changer for India. Some of the world's leading economies including the USA, France, Germany, Ireland, Japan, Singapore, Taiwan and China besides a number of developing economies like Malaysia and Israel have their own fabs. These fabs continue to contribute significantly to the growth and development of the economy of their respective countries and we hope that this would be the case in India as well."
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