Broadcom releases satellite-constellation location IC

Broadcom Corporation has introduced a Global Navigation Satellite System (GNSS) chip, designated BCM47531, that generates positioning data from five satellite constellations simultaneously (GPS, GLONASS, QZSS, SBAS and BeiDou), totaling 88 satellites. The newly added Chinese BeiDou constellation increases the number of satellites available to a smartphone, enhancing navigation accuracy, particularly in urban settings where buildings and obstructions can cause interference.

The company’s new GNSS SoC is based on its widely deployed architecture that reduces the “time to first fix” (TTFF) and allows smartphones to quickly establish location and rapidly deliver mapping data. The SoC also features a tri-band tuner that enables smartphones to receive signals from all major navigation bands (GPS, GLONASS, QZSS, SBAS, and BeiDou) simultaneously.

The BCM47531 platform is available with Broadcom’s Location Based Services (LBS) technology that delivers satellite assistance data to the device and provides an initial fix time within seconds, instead of the minutes that may be required to receive orbit data from the satellites themselves.

The BCM47531 brings a number of powerful features to the table:

• Simultaneous support of five constellations (GPS, GLONASS, QZSS,SBAS and BeiDou) allows for position calculations based on measurements from any of 88 satellites.
• Broadcom's tri-band tuner brings the ability to receive all navigation bands, GPS (which includes QZSS and SBAS), GLONASS and BeiDou simultaneously to the commercial GNSS market without having to reconfigure and hop between bands.
• Utilizes BeiDou signals for up to 2x improved positioning accuracy.
• Best-in-class Assisted GNSS (AGNSS) data available worldwide from Broadcom's hosted reference network.
• Allows a device to interchangeably use the best signal from any satellite regardless of the constellation, ensuring better accuracy in urban and mountainous environments.
• Features advanced digital signal processing for interference rejection that enables satellite signal search and tracking during LTE transmission.
• Leverages Broadcom's connectivity solutions including Wi-Fi, Bluetooth Smart, Near Field Communications (NFC), Instant Messaging System (IMES) and handset inertial sensor data for best indoor/outdoor location.

India Plans To Build 2 Wafer Fabs

The government of India on Thursday approved "in principle" a plan to construct and equip two wafer fabrication facilities in the country, in a move designed to reduce India's reliance on imported semiconductors. Two consortia will go ahead with the twin fab projects. One is led by STMicroelectronics, an integrated device manufacturer, and the other is spearheaded by Tower Semiconductor, a silicon foundry. These companies will add their names to list of VLSI companies in India and boost the manufacturing capability.

"The Cabinet has given in-principle approval for setting up of semiconductor wafer fabrication manufacturing facilities," Information and Broadcasting Minister Manish Tewari told reporters after a meeting of the Union Cabinet, chaired by Prime Minister Manmohan Singh.

After considering proposals from two consortia, the government took the decision. The government received proposals from two consortiums to set up chip fabrication units in the country. One was led by Israel's Tower Jazz and the other was led by Geneva–based chipmaker STMicroelectronics.

Israel-based foundry chipmaker Tower Semiconductor Ltd, which operates under the brand name TowerJazz, partnered with IBM and Indian infrastructure conglomerate Jaypee Associates to build and operate a 300mm chip facility in India. On the other hand, STMicroelectronics partnered with Hindustan Semiconductor Manufacturing Corp. (HSMC).

Welcoming the government's decision, India Electronics & Semiconductor Association (IESA) President PVG Menon said, "The IESA deems the fab a highly strategic game changer for India. Some of the world's leading economies including the USA, France, Germany, Ireland, Japan, Singapore, Taiwan and China besides a number of developing economies like Malaysia and Israel have their own fabs. These fabs continue to contribute significantly to the growth and development of the economy of their respective countries and we hope that this would be the case in India as well."

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How 450mm wafers will change the semiconductor industry

The semiconductor industry's transition to making chips on 450-millimeter wafers is better described as a "transformation," Jonathan Davis of Semiconductor Equipment and Materials International writes. "The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia," he writes, adding, "However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational."

Even for the segments that continue manufacturing semiconductor devices on 300mm and 200mm silicon wafers, the industry will change dramatically with the introduction of 450mm wafer processing. The 450mm era will impact industry composition, supply chain dynamics, capital spending concentration, future R&D capabilities and many other facets of today’s semiconductor manufacturing industry — not the least of which are the fabs, wafers and tools with which chips are made.

The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia.   For those reasons, the evolutionary tone of “transition” seems appropriate. However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational.

No transformation occurs in isolation and other factors will contribute to the revolutionary qualities of 450mm.  Market factors, new facilities design, next generation processing technology, the changing dynamics of node development and new materials integration will simultaneously affect the industry landscape.

While reading about the implications of 450mm is valuable, I believe that there is much to learn by being a part of the discussion. How is this future transformation being envisioned and acted on today?  I hope that you will join us — at our “live” event, where you will have the opportunity to hear first-hand information… direct from well-informed experts in the industry.

Potential revisions in the 450mm wafer specification are under consideration.  At least two issues are currently being evaluated by the industry and both portend significant ramifications for wafer suppliers, equipment makers and those technologies that interface with the wafer.

First, the wafer orientation method may be revised to eliminate the orientation “notch” on the perimeter of the substrate. The notch was introduced in the 300mm transition as an alternative to the flat.  However, both equipment suppliers and IC makers, through a constructive and collaborative dialog, have concluded that eliminating the notch can potentially improve the die yield, tool performance and cost.

Secondly, reduction of the wafer edge exclusion area — that peripheral portion of the silicon on which no viable device structure occurs — also offers potential yield advantages.  The current 450mm wafer specification (SEMI E76-0710), originally published in 2010, calls for a 2mm edge exclusion zone.  IC makers believe that reduction of this area to a 1.5mm dimension offers the cost equivalence of a 1 percent yield increase.  Though a percent may sound trivial, it is represents substantial increased value over time.

Along with cost and efficiency improvements, IC makers and consortia driving the transition to 450mm manufacturing expect to achieve similar or better environmental performance. Larger footprints and resource demands from 450mm facilities in conjunction with mandates for environmentally aware operations are compelling fabs and suppliers to consider sustainability and systems integration at greater levels than ever before.

Experts in fab facilities, energy, water and equipment engineering will discuss the implications of 450mm to environment, health and safety during the SEMICON West 450mm Manufacturing EHS Forum on Wednesday, July 10.

Included in the presentations are perspectives from the Facility 450 Consortium (F450C) including Ovivo, Edwards and M+W Group.  A holistic Site Resource Model that provides semiconductor manufacturers visibility into effective reduction of total energy and water demands for individual systems, as well as for the entire facility will be reviewed by CH2M Hill. The model is an integrated analytical approach to assess and optimize a semiconductor facility’s thermal energy, electrical energy, and water demand, as well as the cost associated with these resources.

3D IC market to see stable growth through 2016

The global 3D integrated circuit market is forecast to grow by 19.7 percent between 2012 and 2016, with the major growth driver being strong demand for memory products, particularly flash memory and DRAM.

3D integrated circuits help improve the performance and reliability of memory chips, and as an added benefit the resulting chips are smaller and cheaper. However, chips based on 3D circuits face thermal conductivity problems which might pose a challenge to further growth.

According to Infiniti Research, the biggest 3D IC vendors at the moment are Advanced Semiconductor Engineering (ASE), Samsung., STMicroelectronics and Taiwan Semiconductor Manufacturing Co. (TSMC). IBM, Elpida, Intel and Micron are also working on products based on 3D ICs.

Intel was a 3D IC pioneer and it demoed a 3D version of the Pentium 4 back in 2004. The overly complicated chip offered slight performance and efficiency improvements over the 2D version of the chip, which really isn't saying much since Prescott-based Pentium 4s were rubbish.

The focus then shifted on memory chips and some academic implementations of 3D processors, but progress has been relatively slow, hence any growth is more than welcome.

French researchers print first ADC on plastic

Millions of tons of food are wasted annually because 'the date'. But the date on the package is always a conservative estimate, so much food that is still good in the waste lands. Would it not be useful if the pack 'taste' of the food is still good? Researchers at the CEA-Liten, Eindhoven University of Technology, STMicroelectronics and University of Catania presented last week in the U.S. technical capstone that makes this possible - a plastic analogue to-digital converter. This gives a plastic sensor circuit of less than one euro cent feasible, which is an acceptable price increase is for example, a bag of potato chips or a piece of meat. The ultra cheap plastic electronics has many potential applications, for example in medicine.

“Organic electronics is still in its infancy, thus only simple digital logic and analogue functions have been demonstrated yet using printing techniques,” said CEA-Liten.

The ADC circuits printed by CEA-Liten include more than 100 n- and p-type transistors and a resistive layer on a transparent plastic sheet. The ADC circuit offers a resolution of 4 bits and has a speed of 2Hz.

The carrier mobility of the printed transistors is higher than the one observed in amorphous silicon, which is widely used in the display industry (CEA technology p-type µp = 1.8 cm²/V.s and n-type µn = 0.5 cm²/V.s).

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6 Ways to Improve Chip Yield Even Before the Project Starts

Early on in Chip projects, yield is not taken very seriously. The common thinking goes –  anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.

1- Know your Yield

Yield has a great deal of impact only if production volume is high. If you plan to manufacture only a few tens of thousands of components, perhaps yield is not the most important topic in your project’s plan.

Yield can be roughly calculated or estimated before the project has even started. Yet, if you have calculate a yield target of 95% there is no reason to invest money and efforts to try improving the yield from (the calculated) 95% to 99% because that would not be possible.  Therefore, it is important that you have calculated your yield and set that as a goal.

2- Consider Foundry Applicability

Semiconductor foundries are not taking any yield losses. It is not the fab responsibility whether your yield is high or low because they sell wafers and not dies. Therefore you should select the foundry the suits best to your Chip domain.

If you chip requires small node geometries go to GLOBALFOUNDRIES, TSMC etc. If you chip needs excellent RF performance go to: IBM, TowerJazz etc. The foundry can help you calculating the wafer yield based on their own process technology. If you can provide them with die size, number of layers, process node and options, they should be able to provide you with a very accurate yield figures for your project.

3- Match Design Team Experience to Your Project

If you have decided to outsource the frond-end and physical design activities to an external vendor, the main yield-related risk here is experience. If the design team does not have the relevant experience that matches your chip project (for instance: RF, High Voltage) you are really wasting your time. Don’t hire analog designer without high voltage experience if you need to design a 120V chip.

4- Select Silicon Proven IPs

More and more companies are shopping for Semiconductor IPs to help reduce time to market and minimize engineering cost. There are many IP vendors with high quality products and some with lower quality. The keyword here is risk minimization. You really want to make sure the IP blocks you are about to purchase and integrate into your chip are bug free and have been silicon proven and qualified for your process. Ask for test results and references.

5- Follow Package Design Rules

For simple QFN packages there are no real concerns besides following the assembly house design rules. However complex packages can reduce yield dramatically. If your chip uses a package that consists of a multilayer substrate with high speed signals, this substrate should be considered as part of the silicon die. Improper routing of high speed signals, for example, will make the substrate performance very marginal and thus result in failures during final test.

6 – Say No to Tight Test Limits, Say Yes to Better Hardware

The only place to measure yield is at the testing phase. And this is done by the ATE.

Great ASIC engineers often try to over-engineer the chip design and as a by-product also tighten up the test result criteria. These limits will have direct impact on your profit. Every device that fails to meet limits during the screening process will be scraped. Therefore, don’t create the perfect test specification. Make one that meets your system requirements.

Loadboards, sockets and probecards have different quality levels and therefore different cost. But since these are the actual physical interface between your chip and the tester, you want to make sure they have the right quality and durably to allow solid connectivity to the tester during the test period. Otherwise, lower quality hardware will shave off your yield figures. Sockets for example, have limited number of insertions; you therefore should buy a socket that meets your chip production volume. Bottom-line — don’t compromise on the quality of the hardware interfacing your chip.

There is so much more to write on this topic, we promise to write more articles in the future. Stay tuned.

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IC Package Types :)

The semiconductor industry manufactures a very huge variety of integrated circuits that have different packaging requirements.  Package attributes that are taken into consideration when choosing a package type for a particular semiconductor device include: size, lead count, power dissipation, field operating conditions, and of course, cost.

Popular IC package types used in the semiconductor industry today are presented below.

Types of IC Packages (not shown in scale)

CBGA - Ceramic Ball Grid Array

CCGA - Ceramic Column Grid Array

CerDIP - Ceramic Dual-in-Line Package

CerPack - Ceramic Package

CLCC - Ceramic Leadless Chip Carrier

CPGA - Ceramic Pin Grid Array

CQFP - Ceramic Quad Flat Pack

D2PAK or DDPAK - Dou-ble Decawatt Package

D3PAK - Decawatt Package 3

DFN - Dual Flat No Leads Package

DPAK - Decawatt Package

FBGA - Fine-Pitch Ball Grid Array

JLCC - J-Leaded Ceramic Chip Carrier

LFBGA - Low Profile Fine-Pitch Ball Grid Array

LGA - Land Grid Array

LQFP - Low-Profile Quad Flat Package

MLP - Micro Leadframe Package

MQFP - Metric Quad Flat Package

MSOP - Micro Small Outline Package

PBGA - Plastic Ball Grid Array

PDIP - Plastic Dual-in-Line Package

PLCC - Plastic Leaded Chip Carrier

PPGA - Plastic Pin Grid Array

PQFN - Power Quad Flat No Leads Package

PQFP - Plastic Quad Flat Pack

PSOP - Power Small Outline Package

QFN - Quad Flat No Leads Package

QSOP - Quarter Size Outline Package

SBDIP - Sidebraze Dual-in-Line Package

SC-70 - Small Outline Transistor

SIP - Single-In-Line Package

SOIC - Small Outline IC Package

SOJ - Small Outline J-Lead Package

SOT-23 - Small Outline Transistor

SPDIP - Shrink Plastic Dual-in-Line Package

SSOP - Shrink Small Outline Package

TDFN - Thin Dual Flat No Leads Package

TFBGA - Thin Fine-Pitch Ball Grid Array

TQFN - Thin Quad Flat No Leads Package

TQFP - Thin Quad Flat Pack

TSOP - Thin Small Outline Package

TSSOP - Thin Shrink Small Outline Package

UTDFN - Ultra Thin Dual Flat No Leads Package

UTQFN - Ultra Thin Quad Flat No Leads Package

VFBGA - Very Thin Fine-Pitch Ball Grid Array

VSOP - Very Small Outline Package

XDFN - Extreme Thin Dual Flat No Leads Package

XQFN - Extreme Thin Quad Flat No Leads Package

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