Button-Size Wearable Computer by Intel

It just got a lot easier to build wearable gadgets that aren’t so bulky or awkward.

Intel CEO Brian Krzanich showed off a minuscule computer, dubbed Curie, during a keynote speech at the International Consumer Electronics Show in Las Vegas on Tuesday. Krzanich plucked a button off his blazer before explaining that it contained a Curie demo module.

Curie is a sure sign that hardware makers are eager to build wearable devices of all kinds. It also points to the unwelcome size of many existing smart watches and smart glasses.

Intel’s new device will include a Bluetooth low-energy radio, motion sensors, and components designed to rapidly and precisely differentiate between different types of physical activity. Krzanich said Curie will run “for extended periods of time” on a coin-size battery and would be available in the second half of the year.

Curie appeared much smaller than a postage-stamp-size computer, called Edison, that Krzanich showed off at last year’s CES.

The world’s largest chip maker evidently sees wearables as one of the most important categories in consumer electronics. It’s a belief held by a lot of other companies at CES, where gadgets meant to be worn on the body or clipped to clothing were all over the show floor this year (see “CES 2015: Wearables Everywhere”).

To make it clear that Curie is already functional, the company built a simple step-tracking smartphone app to go with the module Krzanich had on him; at one point he pulled the phone out of his pocket, and its display indicated he’d taken 1,788 steps during the keynote.

As part of its wearables push, Intel has partnered with a number of companies in the fashion and accessories businesses, including Luxottica Group, which is the world’s largest eyeglass maker with brands such as Ray-Ban and Oakley. Krzanich said Luxottica will use Curie to make “truly consumer-friendly” smart glasses—a notoriously tricky thing to do, in part because of the size of components needed to make them work.

Oakley CEO Colin Baden joined Krzanich on stage to talk about wearables, which Oakley has built in the form of devices like ski goggles that include a head-up display. When you put a wearable device on your face, Baden said, it becomes part of your personality. “It’s important the form factor compress so the electronic component of it doesn’t become burdensome,” he said.

OSVVM – Thinking beyond constrained random

What is OSVVM?

OSVVM stands for "Open Source VHDL Verification Methodology". OSVVM is a set of VHDL packages, initially developed by Jim Lewis of Synthworks. OSVVM helps you adopt modern constrained random verification techniques using VHDL.

Constraint random verification approach :

In testbenches, we generally want one each of a large set of test cases (transactions and/or sequences). Uniform randomization does not generate one each. Instead it has a significant amount of repetition. In general, uniform randomization takes O(N*LogN) randomizations to generate N unique test cases. As a result, it repeats Log N test cases. Even for small numbers such 64 test cases, constrained random will generate more than 4X more test cases than needed - actual results will vary with the randomization seed. Constrained random comes with this fundamental problem. Randomization is intended to be uniform over time. However constraint random verification has a number of benefits:

• If you simulate longer, you generate more test vectors.
• You may find bugs due to unexpected combinations of inputs, or extreme input values. With directed testing, it is all too easy just to test what you expect to happen, rather than trying to test what you don't expect to happen.
• Once you have developed an automated test, it can still be used for directed testing.

Still what we need is an approach that only requires O(N) randomizations to generate N unique test cases. Generally these approaches are referred to as being Intelligent Testbenches. Indeed there are some tools out there that handle this. However, when we use a tool based approach we end up with a vendor specific solution. This removes one of the major benefits of a programming language based approach - encounter a issue (pricing or functionality) with one vendor and you can easily switch to another.

What we really need is a methodology for Intelligent Testbenches that is based on a standard language and works on numerous vendor tools.

OSVVM :

VHDL's Open Source VHDL Verification Methodology (OSVVM). OSVVM's methodology leverages the functional coverage you must write when you are using any randomization based approach. Intelligent Coverage™, the main randomization methodology for OSVVM, randomly selects a hole in the coverage and passes this to the stimulus generation process. The stimulus generation process uses this information, perhaps refines it using any methodology (directed, algorithmic, constrained random or file based), and then generates one or more transactions to accomplish generate the item that needs covered.

OSVVM can be used in your current VHDL testbench, in part or in whole as needed.  It allows mixing of our signature “Intelligent Coverage” methodology with other verification methodologies, such as directed, algorithmic, file based, and constrained random. Don’t throw out your existing VHDL testbench or testbench models, re-use them.

There is no new language to learn. There are no specialized “OO” approaches – just plain old VHDL entities and architectures. As a result, it is accessible to RTL designers. In fact, it is our goal to make our testbenches readable to verification (testbench), design (RTL), system, and software engineers.

OSVVM works with any VHDL testbench and is particularly effective when coupled with a transaction based testbench. For us, VHDL and OSVVM are the step beyond constrained random and SystemVerilog. Maybe it is time we update VHDL's acronym to mean Verification and Hardware Design Language.

Intelligent Coverage™ Methodology :

Verification starts with a test plan that identifies all items in a design that need to be tested.  OSVVM, like other advanced methodologies, uses functional coverage to observe conditions on interfaces and within the design to validate that the items identified in the test plan have occurred.  As such, functional coverage helps determine when testing is done.

Unlike other methodologies, in OSVVM’s Intelligent Coverage methodology,  functional coverage is the prime directive – it is where we start our process.  Intelligent Coverage is done in the following steps.

• Write a high fidelity functional coverage (FC) model
• Randomly select a hole in the functional coverage 
• Refine the initial randomization with sequential code 
• Apply the refined sequence (one or more transactions) 
• Observe Coverage

The key point of Intelligent Coverage is that we randomize using the functional coverage. Then, if necessary, we refine the randomization using sequential code and any sequence generation method, including constrained random, algorithmic, directed, or file reading methods.

OSVVM is a Low Cost Solution :

The packages are free. OSVVM works on regular VHDL simulators (such as Mentor’s ModelSim and Aldec’s Active-HDL) without additional licenses. The only special language support required is VHDL-2002 protected types and VHDL-2008 type integer_vector (for older simulators, we have a work around for this).

To learn more about OSVVM, see:

• The OSVVM Community Forum
• SynthWorks' OSVVM Blog
• OSVVM Webinar on July 18th (US time zones)
• OSVVM Webinar on July 18th (European time zones)
• The packages are available here:  OSVVM.zip

OSVVM is an open source VHDL library that is free to use (no license fees) and works with any simulator that supports VHDL-2008 (or VHDL-2002 with a little work).
What is currently in the OSVVM library is only the beginning. Over time, I will be releasing our generic scoreboard package, memory modeling package, and others.

Intel funding to develop printer for blind

A 13-year-old Indian-origin boy has received a huge investment from Intel for developing a low-cost printer for the blind, making him the youngest tech entrepreneur funded by a venture capital firm.

Shubham Banerjee, CEO of the Braille printer maker Braigo Labs, had closed an early round funding with Intel Capital, the company's venture capital arm, last month to develop a prototype of low-cost Braille printer.

But to attend the event, Banerjee had to take the day off from middle school. That’s because he’s just 13 years old — making him, quite possibly, the youngest recipient of venture capital in Silicon Valley history. (He’s definitely the youngest to receive an investment from Intel Capital.)

“I would like all of us to get together and help the visually impaired, because people have been taking advantage of them for a long time,” Banerjee said. “So I would like that to stop.”

By “taking advantage,” Banerjee is referring to the high price of Braille printers today, usually above $2,000. By contrast, Braigo Labs plans to bring its printer to market for less than $500.

Banerjee has invented a new technology that will facilitate this price cut. Patent applications are still pending, so he wouldn’t divulge any of the details. But the technology could also be used to create a dynamic Braille display — something that shows one line of text at a time by pushing small, physical pixels up and down, and which currently costs $6,500, according to Braigo advisor Henry Wedler, who is blind.

Banerjee also figures that volume production will help keep the price low. Currently, Braille printers cost so much because the demand is low, so current manufacturers need to set a high price in order to recoup their costs.

“The truth is that demand is low in the U.S.,” Banerjee told me. But, he added, if you brought the price low enough there would be huge demand outside the U.S.

Banerjee built the version version of his Lego Braille printer for a science fair. He didn’t know anything about Braille beforehand. In fact, he’d asked his parents how blind people read, he said onstage, and they were too busy to answer. “Go Google it,” he said they told him, so he did.

After learning about Braille, he came up with the idea to make a Braille printer. He showed it at his school’s science fair, then later entered it into the Synopsys Science & Technology Championship, where he won first prize, which included a big trophy and a $500 check.

After that, he started getting a lot of attention on his Facebook page. People kept asking him if they could buy one, he said, which led to the idea of creating a company.

Lego was just for the first prototype, by the way: Future versions will be made with more traditional materials.

So how did Intel come to invest in such a young inventor? His father, Niloy, works for Intel — but that’s not exactly how it happened, according to Niloy.

After working with the beta version of Intel Edison (the chip company’s tiny embeddable microprocessor) at a summer camp, Banerjee’s project came to the attention of Intel, which invited him to show off his printer at the Intel Developer Forum. After appearing at IDF, Intel Capital came calling.

Young Banerjee seems composed in front of crowds, which should serve him well. (That’s not surprising, given that Braigo’s website touts coverage on everything from BoingBoing and SlashGear to CNN and NPR.) When asked onstage, in front of 1,000 entrepreneurs, investors, and Intel employees, how he knew that the printer worked even though he doesn’t read Braille, Banerjee answered immediately, “I Googled it.” The crowd laughed.

“I’m happy that I live in Silicon Valley,” Banerjee said. “So many smart people.”

UVM - Driver

The driver is a block whose role is to interact with the DUT. The driver pulls transactions from the sequencer and sends them repetitively to the signal-level interface. This interaction will be observed and evaluated by another block, the monitor, and as a result, the driver’s functionality should only be limited to send the necessary data to the DUT.

In order to interact with our adder, the driver will execute the following operations: control the en_i signal, send the transactions pulled from the sequencer to the DUT inputs and wait for the adder to finish the operation.

So, we are going to follow these steps:

1. Derive the driver class from the uvm_driver base class
2. Connect the driver to the signal interface
3. Get the item data from the sequencer, drive it to the interface and wait for the DUT execution
4. Add UVM macros

In Code 5.1 you can find the base code pattern which is going to be used in our driver.

class simpleadder_driver extends uvm_driver#(simpleadder_transaction);
     `uvm_component_utils(simpleadder_driver)   //Interface declaration
     protected virtual simpleadder_if vif;   function new(string name, uvm_component parent);
          super.new(name, parent);
     endfunction: new   function void build_phase(uvm_phase phase);
          super.build_phase(phase);
     void'(uvm_resource_db#(virtual simpleadder_if)::read_by_name(.scope("ifs"), .name("simpleadder_if"), .val(vif)));
     endfunction: build_phase   task run_phase(uvm_phase phase);
          //Our code here
     endtask: run_phase
endclass: simpleadder_driver

Code 5.1 – Driver component – simpleadder_driver.sv

The code might look complex already but what it’s represented it’s the usual code patterns from UVM. We are going to focus mainly on the run_phase() task which is where the behaviour of the driver will be stated. But before that, a simple explanation of the existing lines will be given:

• Line 1 derives a class named simpleadder_driver from the UVM class uvm_driver. The #(simpleadder_transaction) is a SystemVerilog parameter and it represents the data type that it will be retrieved from the sequencer.

• Line 2 refers to the UVM utilities macro explained on chapter 2.

• Lines 7 to 9 are the class constructor.

• Line 11 starts the build phase of the class, this phase is executed before the run phase.

• Line 13 gets the interface from the factory database. This is the same interface we instantiated earlier in the top block.

• Line 16 is the run phase, where the code of the driver will be executed.

Now that the driver class was explained, you might be wondering: “What exactly should I write in the run phase?”

Consulting the state machine from the chapter 1, we can see that the DUT waits for the signal en_i to be triggered before listening to the ina and inb inputs, so we need to emulate the states 0 and 1. Although we don’t intend to sample  the output of the DUT with the driver, we still need to respect it, which means, before we send another sequence, we need to wait for the DUT to output the result.

To sum up, in the run phase the following actions must be taken into account:

1. 
   
   Get a sequence item
   
   
2. 
   
   Control the en_i signal
   
   
3. 
   
   Drive the sequence item to the bus
   
   
4. 
   
   Wait a few cycles for a possible DUT response and tell the sequencer to send the next sequence item

The driver will end its operation the moment the sequencer stops sending transactions. This is done automatically by the UVM API, so the designer doesn’t need to to worry with this kind of details.

In order to write the driver, it’s easier to implement the code directly as a normal testbench and observe its behaviour through waveforms. As a result, in the next subchapter (chapter 5.1), the driver will first be implemented as a normal testbench and then we will reuse the code to implement the run phase (chapter 5.2).

Chapter 5.1 – Creating the driver as a normal testbench

For our normal testbench we will use regular Verilog code. We will need two things: generate the clock and idesginate an end for the simulation. A simulation of 30 clock cycles was defined for this testbench.

The code is represented in Code 5.2.

//Generates clock
initial begin
     #20;
    forever #20 clk = ! clk;
end   //Stops testbench after 30 clock cyles
always@(posedge clk)
begin
    counter_finish = counter_finish + 1;   if(counter_finish == 30) $finish;
end

Code 5.2 – Clock generation for the normal testbench

The behaviour of the driver follows in Code 5.3.

//Driver
always@(posedge clk)
begin
    //State 0: Drives the signal en_o
    if(counter_drv==0)
    begin
        en_i = 1'b1;
        state_drv = 1;
    end   if(counter_drv==1)
    begin
        en_i = 1'b0;
    end   case(state_drv)
        //State 1: Transmits the two inputs ina and inb
        1: begin
            ina = tx_ina[1];
            inb = tx_inb[1];   tx_ina = tx_ina << 1;
            tx_inb = tx_inb << 1;   counter_drv = counter_drv + 1;
            if(counter_drv==2) state_drv = 2;
        end   //State 2: Waits for the DUT to respond
        2: begin
            ina = 1'b0;
            inb = 1'b0;
            counter_drv = counter_drv + 1;   //After the supposed response, the TB starts over
            if(counter_drv==6)
            begin
                counter_drv = 0;
                state_drv = 0;   //Restores the values of ina and inb
                //to send again to the DUT
                tx_ina <= 2'b11;
                tx_inb = 2'b10;
            end
        end
    endcase
end

Code 5.3 – Part of the driver

For this testbench, we are sending the values of tx_ina and  tx_inb to the DUT, they are defined in the beginning of the testbench (you can see the complete code attached to this guide).

We are sending the same value multiple times to see how the driver behaves by sending consecutive transactions.

After the execution of the Makefile, a file named simpleadder.dump will be created by VCS. To see the waveforms of the simulation, we just need to open it with DVE.

The waveform for the driver is represented on Figure 5.1.

It’s possible to see that the driver is working as expected: it drives the signal en_i on and off as well the DUT inputs ina and inb and it waits for a response of the DUT before sending the transaction again.

Chapter 5.2 – Implementing the UVM driver

After we have verified that our driver behaves as expected, we are ready to move the code into the run phase as seen in Code 5.4.

virtual task drive();
    simpleadder_transaction sa_tx;
    integer counter = 0, state = 0;
    vif.sig_ina = 0'b0;
    vif.sig_inb = 0'b0;
    vif.sig_en_i = 1'b0;   forever begin
        if(counter==0) begin
            //Gets a transaction from the sequencer and
            //stores it in the variable 'sa_tx'
            seq_item_port.get_next_item(sa_tx);
        end   @(posedge vif.sig_clock)
        begin
            if(counter==0) begin
                vif.sig_en_i = 1'b1;
                state = 1;
            end   if(counter==1) begin
                vif.sig_en_i = 1'b0;
            end   case(state)
                1: begin
                    vif.sig_ina = sa_tx.ina[1];
                    vif.sig_inb = sa_tx.inb[1];   sa_tx.ina = sa_tx.ina << 1;
                    sa_tx.inb = sa_tx.inb << 1;   counter = counter + 1;
                    if(counter==2) state = 2;
                end   2: begin
                    vif.sig_ina = 1'b0;
                    vif.sig_inb = 1'b0;
                    counter = counter + 1;   if(counter==6) begin
                        counter = 0;
                        state = 0;   //Informs the sequencer that the
                        //current operation with
                        //the transaction was finished
                        seq_item_port.item_done();
                    end
                end
            endcase
        end
    end
endtask: drive

Code 5.4 - Task for the run_phase()

The ports of the DUT are acessed through the virtual interface with vif.<signal> as can be seen in lines 4 to 6.

Lines 12 and 50 use a special variable from UVM, the seq_item_port to communicate with the sequencer. The driver calls the method get_next_item() to get a new transaction and once the operation is finished with the current transaction, it calls the method item_done(). If the driver calls get_next_item() but the sequencer doesn’t have any transactions left to transmit, the current task returns.

This variable is actually a UVM port and it connects to the export from the sequencer named seq_item_export. The connection is made by an upper class, in our case, the agent. Ports and exports are going to be further explained in chapter 6.0.1.

This concludes our driver, the full code for the driver can be found in the filesimpleadder_driver.sv. In Figure 5.2, the state of the verification environment with the driver can be seen.

Figure 5.2 – State of the verification environment with the driver

UVM - Sequences and sequencers

The first step in verifying a RTL design is defining what kind of data should be sent to the DUT. While the driver deals with signal activities at the bit level, it doesn’t make sense to keep this level of abstraction as we move away from the DUT, so the concept of transaction was created.

A transaction is a class object, usually extended from uvm_transaction or uvm_sequence_item classes, which includes the information needed to model the communication between two or more components.

Transactions are the smallest data transfers that can be executed in a verification model. They can include variables, constraints and even methods for operating on themselves. Due to their high abstraction level, they aren’t aware of the communication protocol between the components, so they can be reused and extended for different kind of tests if correctly programmed.

An example of a transaction could be an object that would model the communication bus of a master-slave topology. It could include two variables: the address of the device and the data to be transmitted to that device. The transaction would randomize these two variables and the verification environment would make sure that the variables would assume all possible and valid values to cover all combinations.

In order to drive a stimulus into the DUT, a driver component converts transactions into pin wiggles, while a monitor component performs the reverse operation, converting pin wiggles into transactions.

After a basic transaction has been specified, the verification environment will need to generate a collection of them and get them ready to be sent to the driver. This is a job for the sequence. Sequences are an ordered collection of transactions, they shape transactions to our needs and generate as many as we want. This means if we want to test just a specific set of addresses in a master-slave communication topology, we could restrict the randomization to that set of values instead of wasting simulation time in invalid values.

Sequences are extended from uvm_sequence and their main job is generating multiple transactions. After generating those transactions, there is another class that takes them to the driver: the sequencer. The code for the sequencer is usually very simple and in simple environments, the default class from UVM is enough to cover most of the cases.

A representation of this operation is shown in Figure 4.1.

Figure 4.1 - Relation between a sequence, a sequencer and a driver

The sequence englobes a group of transactions and the sequencer takes a transaction from the sequence and takes it to the driver.

To test our DUT we are going to define a simple transaction, extended fromuvm_sequence_item. It will include the following variables:

rand bit[1:0] ina
rand bit[1:0] inb
bit[2:0] out

The variables ina and inb are going to be random values to be driven to the inputs of the DUT and the variable out is going to store the result. The code for the transaction is represented in Code 4.1.

class simpleadder_transaction extends uvm_sequence_item;
     rand bit[1:0] ina;
     rand bit[1:0] inb;
     bit[2:0] out;
 
     function new(string name = "");
          super.new(name);
     endfunction: new
 
     `uvm_object_utils_begin(simpleadder_transaction)
     `uvm_field_int(ina, UVM_ALL_ON)
     `uvm_field_int(inb, UVM_ALL_ON)
     `uvm_field_int(out, UVM_ALL_ON)
     `uvm_object_utils_end
endclass: simpleadder_transaction
Code 4.1 – Transaction for the simpleadder

An explanation of the code will follow:

• Lines 2 and 3 declare the variables for both inputs. The rand keyword asks the compiler to generate and store random values in these variables.
• Lines 6 to 8 include the typical class constructor.
• Lines 10 to 14 include the typical UVM macros.

These few lines of code define the information that is going to be exchanged between the DUT and the testbench.

To demonstrate the reuse capabilities of UVM, let’s imagine a situation where we would want to test a similar adder with a third input, a port named inc.

Instead of rewriting a different transaction to include a variable for this port, it would be easier just to extend the previous class to support the new input.

It’s possible to see an example in Code 5.2.

class simpleadder_transaction_3inputs extends simpleadder_transaction;
     rand bit[1:0] inc;
 
     function new(string name = "");
          super.new(name);
     endfunction: new
 
     `uvm_object_utils_begin(simpleadder_transaction_3inputs)
     `uvm_field_int(inc, UVM_ALL_ON)
     `uvm_object_utils_end
endclass: simpleadder_transaction_3inputs
Code 5.2 – Extension of the previous transaction

As a result of the class simpleadder_transaction_3inputs being an extension of  simpleadder_transaction, we didn’t need to declare again the other variables. While in small examples, like this one, this might not look like something useful, for bigger verification environments, it might save a lot of work.

Sequence

Now that we have a transaction, the next step is to create a sequence.

The code for the sequencer can be found in Code 5.3

class simpleadder_sequence extends uvm_sequence#(simpleadder_transaction);
     `uvm_object_utils(simpleadder_sequence)
 
     function new(string name = "");
          super.new(name);
     endfunction: new
 
     task body();
          simpleadder_transaction sa_tx;
 
          repeat(15) begin
               sa_tx = simpleadder_transaction::type_id::create(...
 
               start_item(sa_tx);
                    assert(sa_tx.randomize());
               finish_item(sa_tx);
          end
     endtask: body
endclass: simpleadder_sequence
Code 5.3 - Code for the sequencer

An explanation of the code will follow:

• Line 8 starts the task body(), which is the main task of a sequence
• Line 11 starts a cycle in order to generate 15 transactions
• Line 12 initializes a blank transaction
• Line 14 is a call that blocks until the driver accesses the transaction being created
• Line 15 triggers the rand keyword of the transaction and randomizes the variables of the transaction to be sent to the driver
• Line 16 is another blocking call which blocks until the driver has completed the operation for the current transaction

Sequencer

The only thing missing is the sequencer. The sequence will be extended from the class uvm_sequencer and it will be responsible for sending the sequences to the driver. The sequencer gets extended from uvm_sequencer. The code can be seen on Code 5.4.

typedef uvm_sequencer#(simpleadder_transaction) simpleadder_sequencer;
Code 5.4 – Extension of the previous transaction

The code for the sequencer is very simple, this line will tell UVM to create a basic sequencer with the default API because we don’t need to add anything else.

So, right now our environment has the following structure:

 

Figure 4.2 – State of the verification environment after the sequencer

You might have noticed two things missing:

• How does the sequence connects to the sequencer?
• How does the sequencer connects to the driver

The connection between the sequence and the sequencer is made by the test block, we will come to this later on chapter 10, and the connection between the sequencer and the driver will be explained on chapter 7.

For more information about transactions and sequences, you can consult:

• Accellera’s UVM 1.1 User’s Guide, page 48
• Verification Academy’s UVM Cookbook, pages 188 and 200

UVM–Top Block

In a normal project, the development of the DUT is done separately from the development of the testbench, so there are two components that connects both of them:

• The top block of the testbench
• A virtual interface

The top block will create instances of the DUT and of the testbench and the virtual interface will act as a bridge between them.

The interface is a module that holds all the signals of the DUT. The monitor, the driver and the DUT are all going to be connected to this module.

The code for the interface can be seen in Code 3.1.

interface simpleadder_if;
     logic    sig_clock;
     logic    sig_ina;
     logic    sig_inb;
     logic    sig_en_i;
     logic    sig_out;
     logic    sig_en_o;
endinterface: simpleadder_ifCode 3.1: Interface module – simpleadder_if.sv

After we have an interface, we will need the top block. This block will be a normal SystemVerilog module and it will be responsible for:

• Connecting the DUT to the test class, using the interface defined before.
• Generating the clock for the DUT.
• Registering the interface in the UVM factory. This is necessary in order to pass this interface to all other classes that will be instantiated in the testbench. It will be registered in the UVM factory by using the uvm_resource_db method and every block that will use the same interface, will need to get it by calling the same method. It might start to look complex, but for now we won’t need to worry about it too much.
• Running the test.
  The source for the top block is represented in Code 3.2.

`include "simpleadder_pkg.sv"
`include "simpleadder.v"
`include "simpleadder_if.sv"
 
module simpleadder_tb_top;
     import uvm_pkg::*;
 
     //Interface declaration
     simpleadder_if vif();
 
     //Connects the Interface to the DUT
     simpleadder dut(vif.sig_clock,
                     vif.sig_en_i,
                     vif.sig_ina,
                     vif.sig_inb,
                     vif.sig_en_o,
                     vif.sig_out);
     initial begin
          //Registers the Interface in the configuration block
          //so that other blocks can use it
          uvm_resource_db#(virtual simpleadder_if)::set(.scope("ifs"), .name("simpleadder_if"), .val(vif));
 
          //Executes the test
          run_test();
     end
 
     //Variable initialization
     initial begin
          vif.sig_clock = 1'b1;
     end
 
     //Clock generation
     always
          #5 vif.sig_clock = ~vif.sig_clock;
     endmodule

Code 3.2: Top block – simepladder_tb_top.sv

A brief explanation of the code will follow:

• The lines 2 and 3 include the DUT and the interface into the top block, the line 5 imports the UVM library, lines 11 to 16 connect the interface signals to the DUT.
• Line 21 registers the interface in the factory database with the name simpleadder_if.
• Line 24 runs one of the test classes defined at compilation runtime. This name is specified in the Makefile.
• Line 34 generates the clock with a period of 10 time units. The time unit is also defined in the Makefile.

For more information about interfaces, you can consult the book “SystemVerilog for Verification: A Guide to Learning the TestBench Language Features“, chapter 5.3.

UVM - Defining The Verification Environment

Before understanding UVM, we need to understand verification.

Right now, we have a DUT and we will have to interact with it in order to test its functionality, so we need to stimulate it. To achieve this, we will need a block that generates sequences of bits to be transmitted to the DUT, this block is going to be named sequencer.

Usually sequencers are unaware of the communication bus, they are responsible for generating generic sequences of data and they pass that data to another block that takes care of the communication with the DUT. This block will be the driver.

While the driver maintains activity with the DUT by feeding it data generated from the sequencers, it doesn’t do any validation of the responses to the stimuli. We need another block that listens to the communication between the driver and the DUT and evaluates the responses from the DUT. This block is the monitor.

Monitors sample the inputs and the outputs of the DUT, they try to make a prediction of the expected result and send the prediction and result of the DUT to another block, the scoreboard, in order to be compared and evaluated.

All these blocks constitute a typical system used for verification and it’s the same structure used for UVM testbenches.

You can find a representation of a similar environment in Figure 2.1.

Figure 2.1: Typical UVM testbench

Usually, sequencers, drivers and monitors compose an agent. An agent and a scoreboard compose an environment. All these blocks are controlled by a greater block denominated of test. The test block controls all the blocks and sub blocks of the testbench. This means that just by changing a few lines of code, we could add, remove and override blocks in our testbench and build different environments without rewriting the whole test.

To illustrate the advantage of this feature, let’s imagine a situation where we are testing a another DUT that uses SPI for communication. If, by any chance, we want to test a similar DUT but with I2C instead, we would just need to add a monitor and a driver for I2C and override the existing SPI blocks, the sequencer and the scoreboard could reused just fine.

UVM Classes

The previous example demonstrates one of the great advantages of UVM. It’s very easy to replace components without having to modify the entire testbench, but it’s also due to the concept of classes and objects from SystemVerilog.

In UVM, all the mentioned blocks are represented as objects that are derived from the already existent classes.

A class tree of the most important UVM classes can be seen in Figure 2.2.

Figure 2.2: Partial UVM class tree

The data that travels to and from our DUT will stored in a class derived either from uvm_sequence_item or uvm_sequence. The sequencer will be derived from uvm_sequencer, the driver from uvm_driver, and so on.

Every each of these classes already have some useful methods implemented, so that the designer can only focus on the important part, which is the functional part of the class that will verify the design. These methods are going to addressed further ahead.

For more information about UVM classes, you can consult the document Accellera’s UVM 1.1 Class Reference.

UVM Phases

All these classes have simulation phases. Phases are ordered steps of execution implemented as methods. When we derive a new class, the simulation of our testbench will go through these different steps in order to construct, configure and connect the testbench component hierarchy.

The most important phases are represented in Figure 2.3.

Figure 2.3: Partial list of UVM phases

A brief explanation of each phase will follow:

• The build phase is used to construct components of the hierarchy. For example, the build phase of the agent class will construct the classes for the monitor, for the sequencer and for the driver.

• The connect is used to connect the different sub components of a class. Using the same example, the connect phase of the agent would connect the driver to the sequencer and it would connect the monitor to an external port.

• The run phase is the main phase of the execution, this is where the actual code of a simulation will execute.

• And at last, the report phase is the phase used to display the results of the simulation.

There are many more phases but none of them are mandatory. If we don’t need to have one in a particular class, we can just omit it and UVM will ignore it.

More information about UVM phasing can be consulted in Verification Academy’s UVM Cookbook, page 48.

UVM Macros

Another important aspect of UVM are the macros. These macros implement some useful methods in classes and in variables. they are optional, but recommended.

The most common ones are:

• `uvm_component_utils – This macro registers the new class type. It’s usually used when deriving new classes like a new agent, driver, monitor and so on.

• `uvm_field_int – This macro registers a variable in the UVM factory and implements some functions like copy(), compare() and print().

• `uvm_info – This a very useful macro to print messages from the UVM environment during simulation time.

This guide will not go into much detail about macros, their usage is always the same for every class, so it’s not worth to put much thought into it for now.

More information can be found in Accellera’s UVM 1.1 Class Reference, page 405.

 

SimpleAdder UVM Testbench

After a brief overview of a UVM testbench, it’s time to start developing one. By the end of this guide, we will have the verification environment from the Figure 2.4.

Figure 2.4: SimpleAdder Final Testbench

This guide will begin to approach the top block and the interface (chapter 3), then it will explain what data will be generated with the sequences and sequencers on chapter 4.

Following the sequencers, it will explain how to drive the signals into the DUT and how to observe the response in chapters 5 and 6 respectively.

Subsequently, it will explain how to connect the sequencer to the driver and the monitor to the scoreboard in chapter 7. Then it will show to build a simple scoreboard in chapter 8.

And finally, the test will be executed and analyzed.

The testbench can be run with the execution of a Makefile provided in the repository. As I mentioned previously, this Makefile uses Synopsys VCS but it should be easily modifiable to be executed with any HDL simulator.