Very Large Scale Integration (VLSI)

Wednesday, 5 October 2011

Loadable Counters

Instead of counting from 0, a counter can be made to count from a given initial value. This type of counter is called a loadable counter.

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Counters are generally made up of flip-flops and logic gates. Like flip-flops, counters can retain an output state after the input condition which brought about that state has been removed. Consequently, digital counters are classified as sequential circuits. While a flip-flop can occupy one of only two possible sattes, a counter can have many more than two states. In the case of a counter, the value of a state is expressed as a multidigit binary number, whose `1's and `0's are usually derived from the outputs of internal flip-flops that make up the counter. The number of states a counter may have is limited only by the amount of electronic hardware that is available. The main types of flip-flops used are J-K flip-flops or T flip-flops, which are J-K flip-flops with both J and K inputs tied together. Before that, here's a quick reminder of how a J-K flip-flop works:

J input	K input	Output, Q
0	0	Q
0	1	0
1	0	1
1	1	not Q

T flip-flops are used because set/reset ([1,0] [0,1]) functions are seldom used. Only the "do nothing" and toggle ([0,0] [1,1]) functions are used. Logic gates are used to decide when to toggle which outputs. Below is an example of a synchronous binary counter, implemented using J-K flip-flops and AND gates.

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Monday, 3 October 2011

Intel Drops MeeGo Mobile OS, Backs Tizen Against Android

Linux Foundation and Limo Foundation are rebooting their efforts to compete with Apple and the Android camp by merging MeeGo and Limo into a new operating system called Tizen, with the backing of Intel and Samsung.

Tizen will be a Web-centric operating system for smartphones, tablets, smart TVs, netbooks and in-vehicle infotainment systems. The Linux Foundation will host the project, and plans an initial release in the first quarter of 2012, enabling the first devices to come to market in mid-2012, it said.

The goal is to develop an OS that makes it easy to a run and develop browser-based applications, where most mobile OSes today focus on running applications natively on the phone.

The future belongs to such HTML5-based applications, Imad Sousou, director of Intel's Open Source Technology Center, said in a blog post on the MeeGo website.

HTML5 will play key role in the new operating system -- and it's the reason why a new operating system is needed, rather than an upgrade to an existing one, according to Sousou: "Shifting to HTML5 doesn't just mean slapping a web runtime on an existing Linux, even one aimed at mobile, as MeeGo has been. Emphasizing HTML5 means that APIs not visible to HTML5 programmers need not be as rigid, and can evolve with platform technology and can vary by market segment," Sousou wrote.

In addition to HTML5, Tizen will have integrated support for the Wholesale Applications Community (WAC) web development environment, an operator-backed initiative to develop Web-based, cross-platform applications. WAC wants to let people use one platform to develop and distribute Web-based mobile applications that can run on a multitude of phones, and allow operators to get a piece of the app store boom. Applications based on WAC are distributed and sold via carrier-operated stores.

Over the next couple of months, Intel will be working very hard to make sure that users of MeeGo can easily transition to Tizen, Sousou said, adding that he will be working even harder to make sure that developers of MeeGo can also transition to Tizen.

Since Nokia decided in February to choose Windows Phone over MeeGo, Intel has been without a major hardware partner, but with Tizen it has Samsung on its side. Intel and Samsung will lead the Tizen technical steering team, according to a blog post on the new Tizen website.

With Android backer Google in the process of acquiring its own phone manufacturer, Motorola Mobility, and Nokia forming a close partnership with Microsoft, Samsung has been put in a position where it feels it has to look for alternatives alongside its own operating system, Bada, according to Pete Cunningham, analyst at Canalys.

But challenging Apple and the Android camp, as well as Windows Phone and Research In Motion, seems to be an almost impossible task. So far, Linux-based projects such as MeeGo and Limo have failed to make their mark, and many think this time will be no different.

"Samsung and Intel create alternative to Android. Really, another fork? This'll end well...," analyst Rob Enderle wrote on Twitter.

Cunningham agrees: "Frankly, Limo has been around for years and achieved nothing. MeeGo has shown promise, but has been slow moving. If you look at that there isn't a lot of hope for [Tizen], but it would be foolish to write off any platform coming to market," he said.

25th International conference on VLSI Design to bring back VLSI Industry into Spotlight

One of the key features of this Silver Jubilee conference is the ‘Student Project Contest’ of ‘Students Forum’ in which over 1000 students are expected to participate.

The 25th International conference on VLSI Design and 11th International Conference on Embedded Systems will be held at HICC, Hyderabad from January 7-11, 2012. This Silver Jubilee conference expects to bring back the spotlight to Hyderabad that hosts the finest multinational players in VLSI Design and Embedded Systems.

One of the key features of this Silver Jubilee conference is the ‘Student Project Contest’ of ‘Students Forum’ in which over 1000 students are expected to participate. ‘Students Forum’ helps the students know their career pathways and understand the technological trends in the industry. Attractive prizes will be given to the winners of the Student Project Contest. The competition is open to all BTech Grads including final year students. The last day for submission of papers is November 1, 2011.

“Participating students can benefit immensely from this silver jubilee conference,” Dasaradha Gude, Silver Jubilee Conference Convenor of 25th International VLSI Conference and 11th Embedded Systems conference, said. ‘The conference will enable them to meet with industry stalwarts, know the emerging trends in the sector and get clarity in new career opportunities. The ‘Student Paper Project’ Competition will allow the students to showcase their design skills and gain feedback from internationally acknowledged experts in the field.’

The conference also offers a big fellowship programme to support faculty & researchers who are not in a position to arrange for their own funds to attend the conference.

The 5 daylong conferences is expected to attract more than 2000 participants and will cover 2 days tutorial sessions followed by three days of regular paper sessions, special sessions, and embedded tutorials. A Reliability Aware System Design & Test (RASDAT) workshop will also be held. Industry presentation sessions, panel discussions, design contest, student project contest and industrial exhibits round off the program.

This is the third time that Hyderabad will be hosting the International VLSI Design and Embedded Systems Conference in a short span of 5 years. This indicates the strength and vitality of the VLSI & Embedded Systems Industry in Hyderabad.

“The VLSI Industry plays a crucial role in building the Technology Ecosystem and is a great catalyst in creating jobs especially in the software and application development sector” Gude said. Every chip rolled out from the industry brings new jobs for the software, programmers and application development engineers.’ He said Hyderabad is already in the world map with its engineers creating new chip for apple and also developing the first fusion chip.”

“The demand for VLSI Design and Embedded Systems talent has almost doubled over the last few years in the city with the requirement touching from the present level of 2000 to 4000.” JA Chowdary, Silver Jubilee Special Chair, JA Chowdary said while addressing the media in Hyderabad today.

This joint global level conference is a forum for researchers and designers to present and discuss various aspects of VLSI Design (Front-end & Back-end), Electronic Design Automation (EDA), Embedded Systems, and Enabling Technologies. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and Embedded Systems, which underpin the semiconductor industry.

“we expect this silver jubilee conference to bring back the spotlight to Hyderabad’s VLSI Design and Embedded System sector advancement. Our focus this year is on Embedded Solutions for Emerging Markets - Consumer, Energy and Automotive. This is a premier global level annual event that provides a platform for Students, Industry Leaders and Design Experts to discuss the growth strategies in the context of VLSI Design and Embedded Systems both in the region and globally.” Gude added

The Silver Jubilee Conference Special Chair, JA Chowdary in his comments said “The industry faces different complex issues when looking at new opportunity to grow globally both in product design and development as each country poses different challenges. We expect this year’s event will offer great networking and knowledge sharing opportunity not only for industry leaders but also for students, researchers and academicians.”

Keynote addresses by veterans in the industry will highlight the VLSI Design and Embedded Systems Conference. The conference featuring speakers from both design and technology field will give penetrating speeches to all the audience. More details of the conference program session will be released in January, 2012.

The conference is proud to create an annual platform for technical exchanges by experts from all over the world on the advancements in semiconductor research, development, and manufacturing.

Dr. Vishwani Agrawal is the Steering Committee Chair. Mr. J. A. Chowdary is the Silver Jubilee Special Chair. Mr. Dasaradha R Gude is the Silver Jubilee Conference Convener. Mr.Srimat Chakradhar is the General Chair of this Silver Jubilee Conference.

The 2011 Conference successfully attracted about 1000 attendees with a very high-quality program featuring three keynote speeches, two special sessions, invited talks, technical sessions with technical papers presented, and two short courses. Both the contributing and invited papers are of high quality, and are presented by industrial and academic leaders and students from over 10 countries.

Source : India Infoline News Service / 10:39 , Sep 29, 2011

VLSI sector faces acute shortage of engineers

HYDERABAD, SEPT. 27.2011:

Severe shortage of VLSI (Very Large Scale Integration) engineers threatens to deter multinational companies in semiconductor industry to enter India.

“The country could generate 2,000-3,000 VLSI engineers in the last 10 years, whereas the country needs about 10,000 engineers,” said Mr Dasaradha R. Gude, Chairman of SoCtronics Technologies Private Ltd.

Addressing a press conference here on Tuesday, Mr J.A. Chowdary, Chairman of TalentSprint and former Managing Director of NVDIA India, said that acute shortage had resulted in high levels of attrition. “Unless we do something about this, MNCs working in VLSI may shy away from investing in India. Within a short span of time, India could made strides in this area. If we do not act now to improve quality in engineers, we may be killing a golden goose,” he felt.

Besides lack of knowledge in this stream in engineering colleges, costs involved to set up facilities to teach students in VLSI too became an impediment. “It costs Rs 20 lakh to buy software per computer. In India, there is no industry funding of colleges unlike in the West,” Mr Dasaradha said.

Mr Manohar Bommena, Site Leader (Hyderabad) of AMD, said that Hyderabad emerged as a leading player with over 30-40 prominent companies setting up their bases. He, however, felt that it needed a robust ecosystem and industry-academia interaction to address the issue of quality manpower.

INTERNATIONAL MEET:

Prof. Subbarangaiah K, Director of VEDA (VLSI Engineering and Design Automation), said the industry would hold 25th international VLSI Design and 11th Embedded Systems conferences in Hyderabad during January 7 to 11, in Hyderabad.

The conferences would see experts present and discuss VLSI designs, EDA (Electronic Design Automation), embedded systems and enabling technologies.

It would also have a competition for students where their project ideas would be evaluated for prizes.

Source : Business Line

Xilinx Releases Pocket Power Estimator App for the iPhone

Designers who rely on their iPhones as much as their PCs now have a quick and easy way to determine the power consumption of Xilinx's 28nm 7 series Field Programmable Gate Arrays (FPGA). The new Pocket Power Estimator (PPE) application for Apple's iPhone enables designers to see how Xilinx's 28nm programmable platforms stack up to alternatives in delivering the lowest power consumption for their systems. Designers can download the PPE from the Apple App Store today and, for the first time ever, quickly and easily explore what-if-scenarios and get immediate feedback on the estimated power consumption compared to alternatives. For more complex and detailed power analyses, designers can use the ISE® Design Suite's XPower Estimator (XPE) and the XPower Analyzer (XPA) tools.

"Manufacturers of electronic systems across all our market segments are eager to either lower their current power budgets or drive higher system performance within the same power budgets," said Xilinx Distinguished Engineer and resident power 'guru' Matt Klein. "Offering the Power Pocket Estimator (PPE) on one of the most popular smartphone platforms puts power estimation in the hands of busy designers who routinely turn to their iPhone to access information, further enhancing their design productivity."

The PPE app, which can also be used with the iPad, offers an easy-to-use GUI for the quick entering of resource requirements - such as SerDes utilization, DSP, memory, logic capacity and more. Compared to the previous generation 40nm FPGAs, Xilinx 7 series FPGAs deliver about 50 percent lower total power, on average, thanks in part to the HPL (high-performance/low-power) process technology offered by foundry partner TSMC. Further components of the power envelope that drive this total power reduction include 65 percent lower maximum (worst case) static power, 25 percent lower dynamic power, 30 percent lower I/O power, and 60 percent lower transceiver power. The PPE app takes into account these aspects of total power consumption to enable designers to easily obtain a high-level estimate of power usage by functional block, and how it compares to other Xilinx or competing devices. The PPE also includes application reference examples that designers can use as starting points to customize to their own specifications. The first release of the app includes design examples for the wired and wireless communications markets, while future releases will have additional market segment examples and support other Smartphone platforms.

7 Series Low Power Benefits:

The 28 HPL process technology avoids many yield and leakage issues seen with the embedded SiGe process used in the 28nm HP process and delivers a more cost-effective process solution. The 7 series' larger design headroom, resulting in greater voltage headroom enabled by the HPL process, allows the choice of operating voltages at a wider range of values and enables a flexible power/performance strategy. This enables Xilinx to offer the new low power -2L option for every 7 series device, providing mid-speed-grade performance at 45 percent lower static power compared to the commercial offering. The same -2L device can also function at 0.9V core voltage to provide lower power benefit, including 55 percent lower static power and 20 percent lower dynamic power compared the equivalent commercial speed grade offering.

On the design tool side of power optimization, Xilinx introduced the first automated, fine-grained clock-gating solution for FPGAs that can reduce dynamic power by up to 30 percent. This automated capability links to the place and route portion of the standard FPGA design flow and uses a set of innovative algorithms to perform an analysis on all portions of the design to create fine-grain clock-gating or logic-gating signals that neutralize superfluous switching activity. The power benefit of the intelligent clock gating can easily be realized in the PPE app by using the power optimization option. Furthermore, it is important to estimate the power consumption under worst-case conditions. The Xilinx PPE app is designed to provide the estimated total power under max conditions to provide a reasonable and realistic estimate for the respective design scenario.

Availability:

The Xilinx PPE mobile application is free of charge and is available now on the Apple App Store. A version of PPE for Android and other Smartphone platforms will be introduced later this year. To learn more about Xilinx's lower power advantage, view the YouTube video, and link to the PPE App, please visit http://www.xilinx.com/power .

About Xilinx:

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit http://www.xilinx.com/.

Tuesday, 27 September 2011

R-S Flip Flop

The circuit of Fig.1 is called a SR flip-flop or bi-stable. We will consider its truth table, and immediately find that we have a problem. We can construct the table for the three states where at least one input is zero. This is because if any input to a nand gate is zero, the output will be one regardless of the other input, and we can therefore work around the loop to calculate all the values. However when R and S are 1 we cannot immediately calculate P and Q; so the only way we can analyze what happens is to look at the possible values that P and Q could hold. Thus we can expand the truth table to include a further two inputs Pp and Qp where the subscript p indicates the previous value.

S	R	Pp	Qp	P	Q
1	1	0	0	1	1	Unstable
1	1	0	1	0	1	Stable
1	1	1	0	1	0	Stable
1	1	1	1	0	0	Unstable

Here we see that there are two states where P=Pp and Q=Qp (1101 and 1110 respectively). These are therefore stable states. The other two states (1100 and 1111) are unstable, and using the simple model with time delay t will oscillate with a period of 2t. In practice, the circuit will fall into one of the two stable states rather than oscillate, since the time delays of the two nand gates will not be precisely the same. Which state if will finish in is non deterministic. In practice we are not interested in the non-deterministic states, only in the stable ones.

This circuit can be considered to be a one bit memory circuit since Q can be set to one or zero. To see this we need to look at a sequence of inputs as shown in Fig.2. At the third time step we have the input 10 which puts the circuit into a known state and the output Q to 1. That value of Q is memorised and remains as long as the input is kept at 11. At the sixth time step the input 01 forces the output Q to be a 0, and as long as the input is held at 11 this 0 remains. This way of looking at the circuit gives rise to the names of the inputs S for Set and R for Reset, and so this flip flop is usually given the name R-S. The following three points should be noted. We are now describing the behaviour by means of a sequence of inputs, and for this reason, these circuits are referred to a sequential. Secondly, in all the cases of interest for this circuit P=Q'. Thirdly, an R-S flip flop can equivalently be built out of NOR gates.