Intel to Sell Ivy Bridge Late in Q4 2011

CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun, which is a rather significant achievement as there have been apparently no major hiccups in the implementation of its 3D transistor technology. There has always been the question how Intel defines "volume", but vice president Mooly Eden told me years ago that Intel would only consider a production process volume production if it affects "millions" of processors.

Intel also stated that Ivy bridge is on target for a late Q4 "qualification for sale", which means that Intel will be begin shipping final products to its customers in the second half of the quarter. This will allow Intel to maintain its tick-tock cadence and keep the claim that a production shrink has been introduced in yet another uneven year (and so that it can state that its 22 nm chips were released in 2011). Of course, that does not mean that you will be able to buy those chips in 2011. According to Otellini, first Ivy Bridge systems should become available in Spring 2012. As Ivy Bridge is introduced and ramping up, Intel expects that its profit margins will improve as well.

Sandy Bridge has, despite an initial hiccup, worked out well for Intel. The company is on track to report $55 billion of revenue for 2011, up more than $11 billion over 2010.

Intel's Ivy Bridge Platform Enters Volume Manufacturing Ahead of Spring 2012 Product Launches

As noted by Tom's Hardware, Intel announced during its earnings conference call this week that its Ivy Bridge platform has entered volume production, with the company expecting to begin deliveries to computer manufacturers by the second half of this quarter. It will, however, take some time for Ivy Bridge to make its way into shipping products, with Intel's partners shooting for a Spring 2012 debut.

“CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun, which is a rather significant achievement as there have been apparently no major hiccups in the implementation of its 3D transistor technology. There has always been the question how Intel defines "volume", but vice president Mooly Eden told me years ago that Intel would only consider a production process volume production if it affects "millions" of processors.”

Intel had previously outlined its Ivy Bridge roadmap as targeting a launch for the first half of 2012, and so the latest news confirming that the company is on track with its new 3-D transistor technology bodes well for an on-time launch.
Ivy Bridge will offer a number of benefits for Apple's notebook lines, opening up the door to quad-core processors in the 13-inch MacBook Pro and bringing significantly faster graphicsand new OpenCL capabilities to the MacBook Air. Ivy Bridge will also support ultra high resolution displays and Intel has committed to Thunderbolt support alongside USB 3.0 in the platform.
A minor refresh to Apple's MacBook Pro line is expected any time now, with the update set to carry the line through until Ivy Bridge is ready.

Switch Level design of 2x1 Multiplexer in Verilog

Below written is a switch level coding example in verilog. Its a code for 2x1 multiplexer.

module mux2_1(q,d,select); //Declared parameter list
output q; //Outputs are declared
input[1:0]d; //Inputs are declared
input select;
wire w; //Internal nets
not(w,select); //Pre-defined gates are used
cmos c1(q,d[0],w,select);
cmos c2(q,d[1],select,w);
endmodule//End Module

enjoy coding…. !!!!

Verilog Module structure

Below code gives basic structure of a verilog module

module M (P1, P2, P3, P4);

input P1, P2;
output [7:0] P3;
inout P4;
reg [7:0] R1, M1[1:1024];
wire W1, W2, W3, W4;
parameter C1 = "This is a string";

initial
begin : BlockName
// Statements
end

always
begin
// Statements
end

// Continuous assignments...
assign W1 = Expression;
wire (Strong1, Weak0) [3:0] #(2,3) W2 = Expression;

// Module instances...
COMP U1 (W3, W4);
COMP U2 (.P1(W3), .P2(W4));

task T1;
input A1;
inout A2;
output A3;
begin
// Statements
end
endtask

function [7:0] F1;
input A1;
begin
// Statements
F1 = Expression;
end
endfunction

endmodule

Johnson Counter

The Johnson counter, also called the twisted ring counter, is a variation of the ring counter, with the inverse output of the most significant flip-flop passed to the input of the least significant flip-flop. The sequence followed begins with all 0's in the register. The final 0 will cause 1's to be shifted into the register from the left-hand side when clock pulses are applied. When the first 1 reaches the most significant flip-flop, 0's will be inserted into the first flip-flop because of the cross-coupling between the output and the input of the counter.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters
• BCD Counter
• Ring counters

Ring counter

A ring counter is a circular shift register with only one flip-flop being set at any particular time; all others are cleared. The single bit is shifted from one flip-flop to the other to produce the sequence of timing signals.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters
• BCD Counter
• Johnson counters

BCD Counter

A BCD counter counts in binary-coded decimal from 0000 to 1001 and back to 0000. Because of the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight binary count.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters 

• Ring Counter
• Johnson counters