List of VLSI Companies

Today India is home to some of the finest semiconductor companies in the world. The semiconductor companies in India are reputed across the globe for their efficient design, verification, validation and manufacturing related solutions for integrated circuits. Also the government of India on approved a plan to construct and equip two wafer fabrication facilities in India, in a move designed to reduce India's reliance on imported semiconductors. Searching a lot we have come across following list of companies that works in VLSI domain. Do write to us if you find any name that needs to be included in this list.


Accel Technologies Limited
http://www.techaccel.com
http://www.accel-india.com
India,Singapore,UAE,USA

Advanced Micro Devices
http://www.amd.com
MNC

Alcatel Vacuum Technology (I)
http://www.adixen.com

Alliance Semiconductor
http://www.alsc.com
India,USA

Altera Semiconductor (I) Pvt. Ltd.
http://www.altera.com

Altium
http://www.altium.com
Australia, China, France, Germany, Japan, Netherlands, Switzerland, USA

Ammos Software Technologies
http://www.ammostech.com
India

Analog Alchemy GmbH
http://www.analog-alchemy.de
Germany

Analog Devices Inc
http://www.analog.com
MNC

Apache Design Solutions Pvt. Ltd.
http://www.apache-da.com

Applied Materials
http://www.appliedmaterials.com
MNC

ARM Inc
http://www.arm.com
MNC

Atheros Communications, Inc.
http://www.atheros.com
China,India,Taiwan,USA

Atrenta
http://www.atrenta.com
MNC

AustrianMicroSystems (AMS)
http://www.austriamicrosystems.com
Headquartered in Austria-- Semiconductor Foundry

AutoESL Design Technologies
http://www.autoesl.com
USA

Baegan Technologies
http://www.baegan.com
India

Bartronics (I) Limited
http://www.bartronicsindia.com

Beceem Communications
http://www.beceem.com
India,USA

Bharat Electronics Limited
http://www.bel-india.com

BitMapper
http://www.bitmapper.com
India

Bluespec India
http://www.bluespec.com

Broadcom Corporation
http://www.broadcom.com
MNC

cadence
http://www.cadence.com
MNC

Calypto Design Systems
http://www.calypto.com
USA

Carbon Design Systems
http://www.carbondesignsystems.com
Japan, USA

CDAC
http://www.cdac.in
India

CG-CoreEl
http://www.cg-coreel.com
India

Chartered Semiconductor Manufacturing Lt
http://www.charteredsemi.com
China, German, Japan, Singapore, Taiwan, UK, USA

Chiptest
http://www.chiptestinc.com
India, USA

Cir-Q-Tech Tako Technologies Pvt. Ltd.
http://www.cir-q-tech.net

CircuitSutra Technologies
http://www.circuitsutra.com
India

Cirrus Logic Software
http://www.cirrus.com
China, Japan, Singapore, South Korea, Taiwan, UK, USA

Cisco Systems Inc
http://www.cisco.com
MNC

CMR Design Automation Pvt. Ltd.
http://www.cmrda.com

Conexant Systems, Inc.
http://www.conexant.com
India,USA

ControlNet
http://www.controlnetindia.com
India

Cortina Systems
http://www.cortina-systems.com
Canada, China, India, USA

Cortina Systems, Inc.
http://www.cortina-systems.com
Canada,China,India,USA

Cosmic Circuits
http://www.cosmiccircuits.com
India

CoWare India Pvt. Ltd.
http://www.coware.com

Cranes Software International Limited
http://www.cranessoftware.com
bangalore

CriticalBlue
http://www.criticalblue.com
Japan,UK,USA

Cswitch
http://www.cswitch.com Canada, Germany, Japan, UK, USA

Cypress
http://www.cypress.com
MNC

Dafca Inc.
http://www.dafca.com
USA

Denali Software
http://www.denali.com
France, India, Japan, Korea, Singapore, UK, USA

DigiBee Microsystems
http://www.dgbmicro.com
India

Digital Core Design
http://www.dcd.pl

DSP Group
http://www.dspg.com
Israel,USA

D\'gipro Systems Pvt. Ltd.
http://www.dgipro-systems.com

E-Con InfoTech Pvt Ltd
http://www.e-coninfotech.com

eASIC
http://www.easic.com
Israel, JAPAN, Singapore, USA

Edison Semiconductors
http://www.edisonsemiconductor.com

EDWARDS (I) Pvt Ltd
http://www.edwardsvacuum.com

eInfochips
http://www.einfochips.com
India,USA

Embedded Wireless Ltd
http://www.embeddedwireless.com
Malaysia

Emulex Corporation
http://www.emulex.com
India, UK, USA

eon infotech ltd
http://http://www.eoninfotech.com/ INDIA

Epcos AG
http://www.epcos.com
Brazil, Spain, India, Hungary, Austria (Deutschlandsberg), USA, Czech Republic, Malaysia, Singapore and China.

Esterel EDA Technologies SAS
http://www.esterel-eda.com
France

EVE Design Automation Pvt. Ltd.
http://www.eve-team.com

Fabtech Technologies International Pvt L
http://www.fabtecheng.com

Forte Design Systems
http://www.forteds.com
France,Japan,USA

Four-C-Tron
http://www.fourctron.com

Freescale Semiconductor
http://www.freescale.com
MNC

GDA Technologies
http://www.gdatech.com
India, Japan, USA

GE
http://www.ge.com
MNC

Genesis Microchip
http://www.gnss.com
Canada, China, India, Japan, Korea, Singapore, Taiwan, USA

HCL Technologies
http://www.hcltech.com
India

Hellosoft (I) Pvt. Ltd.
http://www.hyd.hellosoft.com

Hindustan Semiconductor Manufacturing In
http://www.hsmcindia.com

Ibiden Singapore Pte Ltd
http://www.ibiden.com

IBM
http://www.ibm.com
MNC

Ikanos Communications
http://www.ikanos.com
India,USA

Imagination Technologies (I) Private Ltd
http://www.imgtec.com

Implantaire Technologies (India) Private
http://www.implantaire.com
Karnataka INDIA

Incide S.A.
http://www.incide-semi.com
Spain

Indrion Technologies (I) Pvt. Ltd.
http://www.indrion.co.in

IndusEdge Innovations Pvt. Ltd.
http://www.indusedgeinnovations.com

Infineon Technologies
http://www.infineon.com
MNC

Infinera
http://www.infinera.com
India,China,Korea,Singapore,UK,USA

Infinity Infotech Parks Ltd
http://www.infinityitpark.com

Ingenient Technologies
http://www.ingenient.com

India, Japan, Korea, USA
Insilica
http://www.insilicainc.com
India,Slovenia,USA

Intel Corporation
http://www.intel.com
MNC

Interra Systems (I) Pvt Ltd.
http://www.interrasystems.com

Intersil Analog Service Pvt.Ltd.
http://www.intersil.com

IPextreme
http://www.ip-extreme.com
Germany, Japan, USA

Ittiam Systems Pvt. Ltd.
http://www.ittiam.com

iWave Systems
http://www.iwavesystems.com Bangalore, Japan

Jeda Technologies
http://www.jedatechnologies.net
China, USA

kasura Technologies
http://www.kasura.com
India

Kausra technologies
http://www.kasura.com/ INDIA

Kawasaki Microelectronics Inc.
http://www.k-micro.com

Kilopass Technology Inc.
http://www.kilopass.com
USA

KLA Tencor Software (I) Pvt. Ltd.
http://www.kla-tencor.com

KPIT Cummins Infosystems
http://www.kpitcummins.com
France, Germany, India, Japan, Korea, Poland, Singapore, UK, USA

Larsen & Toubro Limited
http://www.ltindia.com

Lattice Semiconductor Corporation
http://www.latticesemi.com
China,USA

LIGA Systems
http://www.ligasystems.com USA

Lofru Technologies
http://www.lofru.com/default.aspx

LogicVision
http://www.logicvision.com
Canada, USA

LSI Corporation
http://www.lsi.com
MNC

Magma Design Automation
http://www.magma-da.com
MNC

Marvell Semiconductor
http://www.marvell.com
MNC

Masamb Electronics Systems Pvt. Ltd.
http://www.masamb.com
Registered Office: A-8, Sector -41, Noida-201303, Uttar pradesh(India)
Corporate Office: G-19, Sector -63, Noida-201301, Uttar pradesh(India)
Phone: +91-120-4541900
Maven Silicon
No.74, 4th Cross, Omkara Nagar, Arekere Mico Layout Main Road, Bannerghatta Road, Bangalore - 560076

Maxim Integrated Products
http://www.maxim-ic.com
India, Italy, Netherlands, Philippines, Thailand, Turkey, USA

Mentor Graphics (I) Pvt. Ltd.
http://www.mentor.com

Microchip
http://www.microchip.com
MNC

Mindspeed Technologies, Inc
http://www.mindspeed.com
china,india,japan,taiwan,france,UAE,USA

MindTree Consulting Ltd.
http://www.mindtree.com
Australia, Germany, India, Japan, Singapore, Sweden, UAE, United Kingdom, USA

MIPS Technologies
http://www.mips.com
China, Germany, India, Israel, Japan, Taiwan, UK, USA

Mirafra Technologies
http://www.mirafra.com
INDIA

Mistral Software
http://www.mistralsoftware.com
India, Germany, USA

Montalvo Systems
http://www.montalvosystems.com
India, USA

MosChip Semiconductor Inc
http://www.moschip.com India, USA

Natsem (National Semiconductors)
http://www.national.com
MNC

NEC Electronics Singapore Pvt Ltd
http://www.sg.necel.com

NeoMagic Corporation
http://www.neomagic.com
India, Israel, USA

NetLogic Microsystems
http://www.netlogicmicro.com
India, Taiwan, USA

Nevis Networks
http://www.nevisnetworks.com
China, India, UK, USA

NI Systems (I) Pvt. Ltd.
http://www.ni.com/india

NOMUS COMM-SYSTEMS
http://www.nomus.in
INDIA

Novas
http://www.novas.com
Israel, UK, USA

Novellus Systems (I) Pvt. Ltd.
http://www.novellus.com

nsys
http://www.nsysinc.com
India

Nulife Technology
http://www.nulifetech.com
India, USA

Nvidia Corporation
http://www.nvidia.com
China, England, Finland, France, Germany, India, Japan, Korea,Russia, Taiwan, USA
NVLogic Technologies Pvt Plt
NVLogic Technologies Pvt. Ltd. 16-2-836/47/B, Road #9, Madhavanagar, Saidabad, Hyderabad - 500 059
E-Mail: info@nvlogic.com

NXP
http://www.nxp.com
MNC

OpenSilicon
http://www.open-silicon.com
India,USA

PACT XPP Technologies
http://www.pactxpp.com
Germany,Japan,USA

Patni Computer Systems Limited
http://www.patni.com

Perfectus Technology
http://www.perfectus.com
India,USA

Perftrends
http://www.perftrends.com
India, USA

Philips Semiconductors
http://www.philips.com
MNC

PMC-Sierra
http://www.pmc-sierra.com
Canada, China, India, Israel, USA

Posedge
http://www.posedge.com

ProcSys
http://www.procsys.com
India

ProDesign
http://www.prodesign-europe.com
Germany,USA

PulseCore
http://www.pulsecoresemi.com
India, Taiwan, USA

Qualcomm
http://www.qualcomm.com
China, Germany, India, Israel, Japan, South Korea, Netherland, singapore, Taiwan, UK, USA

Qualcorelogic
http://www.qualcorelogic.com
India, USA

QuickLogic Corporation
http://www.quicklogic.com
Canada, India, USA

Rambus Inc.
http://www.rambus.com
Germany, India, Japan, Korea, Taiwan, USA

STMicroelectronics
http://www.st.com
MNC

Stretch Inc.
http://www.stretchinc.com Germany, Japan, USA

SYkio Technologies
http://www.sykiotech.com
India

Symmid Semiconductor Technology
http://www.symmidsemi.com
USA

Synfora
http://www.synfora.com
France, India, Japan, Korea, Taiwan, USA

Synopsys (I) Pvt. Ltd.
http://www.synopsys.com

Tallika Technologies Pvt Ltd
http://www.tallika.com

Tata Consultancy Services Ltd.
http://www.tcs.com

TATA ELXSI LTD
http://www.tataelxsi.com

TechForce
http://www.tforceinc.com
India, USA

Tensilica Technologies
http://www.tensilica.com
India,USA

Teranetics
http://www.teranetics.com
India, USA

TES Electronics Soloutions
http://www.tesbv.com
India, France, Germany, Malaysia, UK, USA

Tessolve Services Pvt. Ltd.
http://www.tessolve.com

Texas Instruments
http://www.ti.com
MNC

Toshiba Embedded Software (India) Pvt Lt
http://www.toshiba-tesi.com

Transwitch
http://www.transwitch.com
China, India, Israel, Italy, Belgium, France, Germany, Taiwan, UK

TriQuint Semiconductor
http://www.triquint.com
China, Costa Rico, Germany, USA

Tundra Semiconductor Corp.
http://www.tundra.com
Canada, China, India, Japan, Korea, UK, USA

UMC
http://www.umc.com
Japan, Netherlands, Singapore, Taiwan, USA

Velankani Information Systems
http://www.velankani.com
India, USA

VeriSilicon
http://www.verisilicon.com
China, France, Japan, Korea, Taiwan

VinChip Systems Inc
http://www.vinchip.com
USA

Virage Logic Corporation
http://www.viragelogic.com
Armenia, Germany, India, Israel, Japan, UK, USA

Vitesse
http://www.vitesse.com
USA

VLSI Plus
http://www.vlsiplus.com
Israel

waveaxis technologies
http://www.waveaxis.com
INDIA

Wipro Technologies
http://www.wipro.com
MNC

XILINX
http://www.xilinx.com MNC

XtremeEDA Corporation
http://www.xtreme-eda.com
Canada

Yogitech SPA
http://www.yogitech.com
Italy

Zilog
http://www.zilog.com
India, Philippines, UK, USA
Zoran Corporation
http://www.zoran.com
canada, China, Germany, Israel, Japan, Korea, Taiwan, UK, USA

Pronesis Technologies
http://pronesistech.com/
Ahmedabad-India, USA

ROHM Semiconductor
http://www.rohm.com/web/global/
MNC

SiValley Technologies Pvt. Ltd
http://www.sivalleytech.com/
Bangalore.
email : info@sivalleytech.com
Phone:  +91-80 4095 7500

Ineda Systems Pvt. Ltd
http://inedasystems.com/
Hyderabad, Pune

The Brainy CPU - Mimicking the brain, in silicon

What would you say if your smart device started self-learning different languages and became your smart personal translator? What if it had completed a study of quantum mechanics and became your virtual tutor (my wishful thinking to pass a Christmas exam)… :)

Fabricated analog very-large-scale integration (VLSI) chip used to mimic neuronal processes involved in memory and learning. (Image: Guy Rachmuth)

MIT researchers have taken this major step by designing a computer chip that mimics how the brain?s neurons perceive new information. This phenomenon is known as ?neuroplasticity? and is an ability of the brain related to learning and memory.

There are about 100 billion neurons in the brain, each of which forms synapses with many other neurons. A synapse is the gap between two neurons (known as the presynaptic and postsynaptic neurons). The presynaptic neuron releases neurotransmitters, such as glutamate and GABA, which bind to receptors on the postsynaptic cell membrane, activating ion channels. Opening and closing those channels changes the cell's electrical potential. If the potential changes dramatically enough, the cell fires an electrical impulse called an action potential.

All of this synaptic activity depends on the ion channels, which control the flow of charged atoms such as sodium, potassium and calcium. Those channels are also key to two processes known as long-term potentiation (LTP) and long-term depression (LTD), which strengthen and weaken synapses, respectively.

A silicon chip can simulate the activity of a single brain synapse - a connection between the presynaptic and postsynaptic neurons relaying information flow - with 400 transistors.

How does the chip work?

In the chip, the transistors could mimic activities of different ion channels. Unlike conventional chips operating in on/off mode (digital), current through the transistors on this new brain chip will flow in analog fashion, driven by a gradient of electrical potential in the same manner of ions flowing through ion channels in a cell. Chi-Sang Poon, a principal research scientist in the Harvard-MIT Division of Health Sciences and Technology, mentioned that it is possible to capture every ionic process going on in a neuron by tweaking the parameters of the circuit to match specific ion channels.

Future applications

There are quite a number of future applications using this brainy chip. It would allow the building of systems to model specific neural functions, such as the visual processing system. Interfacing with biological systems, allowing communication between neural prosthetic devices (e.g. artificial retinas) and the brain would also be possible. The technology would help neuroscientists learn more about how the brain works, and becoming a foundation for artificial intelligence devices. The chip would ultimately lead to a virtual translator and a tutor (I am not giving up on them yet!).

Source: http://www.nanowerk.com/news/newsid=23397.php

Boolean Algebra Simplified

Once one has defined a notation for an algebra, the rules to manipulate expressions follow. The most simple are the rules that concern the unary operator NOT:

(A')' = A

A • A' = 0

A + A' = 1

 

General rules like the distributive, commutative, and associative rules hold for the AND and OR binary operators (except one weird one) so that:

Distributive:

A•(B+C) = A•B + A•C

A+(B•C) = (A+B)•(A+C) (the weird one!)

 

Commutative:

A•B = B•A

A+B = B+A

Associative: (A•B)•C = A•(B•C)

(A+B)+C = A+(B+C)

 

In addition, there are simplification rules for Boolean equations. There are three important groups of simplification rules.

The first one uses just one variable:

A•A = A

A+A = A

 

The second group uses Boolean constants 0 and 1:

A • 0 = 0

A • 1 = A

A + 0 = A

A + 1 = 1

 

The third group involves two or more variables and contains a large number of possible simplification rules (or theorems) such as:

 

A + A•( B ) = A

( proof: A + A•B = A•(1+B) = A•1 = A )

 

Note that in this expression either A or B may stand for any complex Boolean expression.

There are two important rules which constitute de Morgan's theorem:

(A+B)' = A' • B'

(A•B)' = A' + B'

 

This theorem is widely used in Boolean logic design. Stated in words it is: To "invert" (negate) a Boolean expression, you replace the AND operator with the OR operator (or vice versa) and invert the individual terms. The theorem holds for any number of terms, so:

 

(A+B+C)' = ( (A+B)+C)' = ( (A+B)' )•C' = A'•B'•C'

and similarly:

(A•B•C•....•X)' = A' + B' + C' + ......+ X'

 

You may have noticed by now that rules are often given in pairs. It makes sense that in a binary system there is some kind of symmetry between the two operators. For Boolean algebra this symmetry is called Duality. Every equation has its dual which one can generate by replacing the AND operators with ORs (and vice versa) and the constants 0 with 1s (and vice versa).

 

For example, the dual equation of the important simplifying rule:

A + A•B = A

is:

A•(A+B) = A (proof: A•A + A•B = A + A•B = A )

 

Do not mix up or get confused between a dual expression which is generated by the above rules and the complement (or inverted) expression which is generated by applying the NOT operator. The rules are similar, but they mean very different things.

 

Finally, let us consider the proposition (I am not taking an umbrella), or:

 

(U)' = ( C'•(W+R) )'

Apply de Morgan's theorem

U' = (C')' + (W+R)'

Apply de Morgan's theorem again

U' = (C')' + W'•R'

And simplify

U' = C + W'•R'

Comparison Of VHDL and Verilog

There are now two industry standard hardware description languages, VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison. For example, a designer might have a model of a PCI bus interface written in VHDL, but wants to use it in a design with macros written in Verilog.

VHDL (Very high speed integrated circuit Hardware Description Language) became IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076 1993". The Verilog hardware description language has been used far longer than VHDL and has been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in December 1995.

There are two aspects to modeling hardware that any hardware description language facilitates; true abstract behavior and hardware structure. This means modeled hardware behavior is not prejudiced by structural or design aspects of hardware intent and that hardware structure is capable of being modeled irrespective of the design's behavior.

VHDL/Verilog compared & contrasted

This section compares and contrasts individual aspects of the two languages; they are listed in alphabetical order.

Capability

Hardware structure can be modeled equally effectively in both VHDL and Verilog. When modeling abstract hardware, the capability of VHDL can sometimes only be achieved in Verilog when using the PLI. The choice of which to use is not therefore based solely on technical capability but on:

personal preferences, EDA tool availability, commercial, business and marketing issues

The modeling constructs of VHDL and Verilog cover a slightly different spectrum across the levels of behavioral abstraction; see Figure 1.

• Figure 1. HDL modeling capability

Compilation

VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types

VHDL. A multitude of language or user defined data types can be used. This may m ean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

Easiest to Learn

Starting with zero knowledge of either language, Verilog is probably the easiest to grasp and understand. This assumes the Verilog compiler directive language for simulation and the PLI language is not included. If these languages are included they can be looked upon as two additional languages that need to be learned. VHDL may seem less intuitive at first for two primary reasons. First, it is very strongly typed; a feature that makes it robust and powerful for the advanced user after a longer learning phase. Second, there are many ways to model the same circuit, specially those with large hierarchical structures.

Forward and back annotation

A spin-off from Verilog is the Standard Delay Format (SDF). This is a general purpose format used to define the timing delays in a circuit. The format provides a bidirectional link between, chip layout tools, and either synthesis or simulation tools, in order to provide more accurate timing representations. The SDF format is now an industry standard in it's own right.

High level constructs

VHDL. There are more constructs and features for high-level modeling in VHDL than there are in Verilog. Abstract data types can be used along with the following statements:

* package statements for model reuse,

* configuration statements for configuring design structure,

* generate statements for replicating structure,

* generic statements for generic models that can be individually characterized, for example, bit width.

All these language statements are useful in synthesizable models.

Verilog. Except for being able to parameterize models by overloading parameter constants, there is no equivalent to the high-level VHDL modeling statements in Verilog.

Language Extensions

The use of language extensions will make a model non standard and most likely not portable across other design tools. However, sometimes they are necessary in order to achieve the desired results.

VHDL. Has an attribute called 'foreign that allows architectures and subprograms to be modeled in another language.

Verilog. The Programming Language Interface (PLI) is an interface mechanism between Verilog models and Verilog software tools. For example, a designer, or more likely, a Verilog tool vendor, can specify user defined tasks or functions in the C programming language, and then call them from the Verilog source description. Use of such tasks or functions make a Verilog model nonstandard and so may not be usable by other Verilog tools. Their use is not recommended.

Libraries

VHDL. A library is a store for compiled entities, architectures, packages and configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins as an interpretive language.

Low Level Constructs

VHDL. Simple two input logical operators are built into the language, they are: NOT, AND, OR, NAND, NOR, XOR and XNOR. Any timing must be separately specified using the after clause. Separate constructs defined under the VITAL language must be used to define the cell primitives of ASIC and FPGA libraries.

Verilog. The Verilog language was originally developed with gate level modeling in mind, and so has very good constructs for modeling at this level and for modeling the cell primitives of ASIC and FPGA libraries. Examples include User Defined Primitive s (UDP), truth tables and the specify block for specifying timing delays across a module.

Managing large designs

VHDL. Configuration, generate, generic and package statements all help manage large design structures.

Verilog. There are no statements in Verilog that help manage large designs.

Operators

The majority of operators are the same between the two languages. Verilog does have very useful unary reduction operators that are not in VHDL. A loop statement can be used in VHDL to perform the same operation as a Verilog unary reduction operator. VHDL has the mod operator that is not found in Verilog.

Parameterizable models

VHDL. A specific bit width model can be instantiated from a generic n-bit model using the generic statement. The generic model will not synthesize until it is instantiated and the value of the generic given.

Verilog. A specific width model can be instantiated from a generic n-bit model using overloaded parameter values. The generic model must have a default parameter value defined. This means two things. In the absence of an overloaded value being specified, it will still synthesize, but will use the specified default parameter value. Also, it does not need to be instantiated with an overloaded parameter value specified, before it will synthesize.

Procedures and tasks

VHDL allows concurrent procedure calls; Verilog does not allow concurrent task calls.

Readability

This is more a matter of coding style and experience than language feature. VHDL is a concise and verbose language; its roots are based on Ada. Verilog is more like C because it's constructs are based approximately 50% on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL. Although an existing programmer of both C and Ada may find the mix of constructs somewhat confusing at first. Whatever HDL is used, when writing or reading an HDL model to be synthesized it is important to think about hardware intent.

Structural replication

VHDL. The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately.

Verilog. There is no equivalent to the generate statement in Verilog.

Test harnesses

Designers typically spend about 50% of their time writing synthesizable models and the other 50% writing a test harness to verify the synthesizable models. Test harnesses are not restricted to the synthesizable subset and so are free to use the full potential of the language. VHDL has generic and configuration statements that are useful in test harnesses, that are not found in Verilog.

Verboseness

VHDL. Because VHDL is a very strongly typed language models must be coded precisely with defined and matching data types. This may be considered an advantage or disadvantage. However, it does mean models are often more verbose, and the code often longer, than it's Verilog equivalent.

Verilog. Signals representing objects of different bits widths may be assigned to each other. The signal representing the smaller number of bits is automatically padded out to that of the larger number of bits, and is independent of whether it is the assigned signal or not. Unused bits will be automatically optimized away during the synthesis process. This has the advantage of not needing to model quite so explicitly as in VHDL, but does mean unintended modeling errors will not be identified by an analyzer.

Designing RTL hardware models in VHDL and Verilog

The models have additional inputs and outputs over and above that of the algorithmic models. They are inputs Clock, Reset_N and Load, and the output Done. When Load is at logic 1 it signifies input data is available on inputs A and B, and are loaded into separate registers whose output signals are called A_hold and B_ hold. The extra output signal, Done, switches to a logic 1 to signify the greate st common divisor has been computed. It takes a number of clock cycles to comput e the GCD and is dependent upon the values of A and B.

The models are broken down into three process (VHDL)/always (Verilog) statements.

First process/always statement LOAD_SWAP. Infers two registers which operate as follows:

1) When Reset_N is at a logic 0, A_hold and B_hold are set to zero.

2) When not 1) and Load is at logic 1, data on A and B is loaded into A_hold and B_hold.

3) When not 1) or 2) and A_hold is less than B_hold, values on A_hold and B_hold are swapped, that is, A_hold and B_hold are loaded into B_hold and A_hold respectively.

4) When not 1), 2) or 3), A_hold is reloaded, that is, it keeps the same value. The value of A_hold - B_hold, from the second process/always statement, is loaded into B_hold.

Second process/always statement SUBTRACT_TEST. The first if statement tests to see if A_hold is greater than or equal to B_hold. If it is, the subtraction, A_hold - B_hold, occurs and the result assigned to A_New ready to be loaded into B_hold on the next rising edge of the clock signal. If A_hold is less than B_hold, then subtraction cannot occur and A_New is assigned the value B_hold so that a swap occurs after the next rising edge of the clock signal. The second if statement checks to see if the value of B_hold has reached zero. If it has, signal Done is set to logic 1 and the value of A_ hold is passed to the output Y through an inferred multiplexer function.

It is a requirement of the problem to synthesize the generic model with 8-bit bus signals. This is easily achieved in Verilog model by setting the default parameter value Width to 8. This means it does not need to be separately instantiat ed before it can be synthesized and have the correct bit width. This is not the case in VHDL, which uses a generic. The value of the generic is only specified when the model is instantiated. Although the VHDL model will be instantiated in the test harness, the test harness is not synthesized. Therefore, in order to synthesize an 8-bit GCD circuit a separate synthesizable model must be used to instantiate the RTL level model which specifies the generic, Width, to be 8. The simulation test harness does not need to use this extra model as it too, will specify the generic, Width, to be 8.

VHDL RTL model
library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
entity GCD is
generic (Width: natural);
port (Clock,Reset,Load: in std_logic;
   A,B:   in unsigned(Width-1 downto 0);
   Done:  out std_logic;
   Y:     out unsigned(Width-1 downto 0));
end entity GCD;
architecture RTL of GCD is
   signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0);
   signal A_lessthan_B: std_logic;
begin
----------------------------------------------------
-- Load 2 input registers and ensure B_Hold < A_Hold
---------------------------------------------------
LOAD_SWAP: process (Clock)
begin
   if rising_edge(Clock) then
     if (Reset = '0') then
       A_Hold <= (others => '0');
       B_Hold <= (others => '0');
     elsif (Load = '1') then
       A_Hold <= A;
       B_Hold <= B;
     else if (A_lessthan_B = '1') then
       A_Hold <= B_Hold;
       B_Hold <= A_New;
     else A_Hold <= A _New;
     end if;
   end if;
end process LOAD_SWAP;
SUBTRACT_TEST: process (A_Hold, B_Hold)
begin
   -------------------------------------------------------
   -- Subtract B_Hold from A_Hold if A_Hold >= B_Hold
   ------------------------------------------------------
   if (A_Hold >= B_Hold) then
      A_lessthan_B <= '0';
      A_New <= A_Hold - B_Hold;
   else
      A_lessthan_B <= '1';
      A_New <= A_Hold;
   end if;
   -------------------------------------------------
   -- Greatest common divisor found if B_Hold = 0
   -------------------------------------------------
   if (B_Hold = (others => '0')) then
      Done <= '1';
      Y <= A_Hold;
   else
      Done <= '0';
      Y <= (others => '0');
   end if;
end process SUBTRACT_TEST;
end architecture RTL;
Verilog RTL model
module GCD (Clock, Reset, Load, A, B, Done, Y);
parameter Width = 8;
input Clock, Reset, Load;
input [Width-1:0] A, B;
output Done;
output [Width-1:0] Y;
reg A_lessthan_B, Done;
reg [Width-1:0] A_New, A_Hold, B_Hold, Y;
//-----------------------------------------------------
// Load 2 input registers and ensure B_Hold < A_Hold
//-----------------------------------------------------
always @(posedge Clock)
    begin: LOAD_SWAP
       if (Reset) begin
           A_Hold = 0;
           B_Hold = 0;
       end
       else if (Load) begin
           A_Hold = A;
           B_Hold = B;
       end
       else if (A_lessthan_B) begin
           A_Hold = B_Hold;
           B_Hold = A_New;
       end
       else
           A_Hold = A_New;
    end
always @(A_Hold or B_Hold)
   begin: SUBTRACT_TEST
      //--------------------------------------------------
      // Subtract B_Hold from A_Hold if A_Hold >= B_Hold
      //--------------------------------------------------
      if (A_Hold >= B_Hold) begin
         A_lessthan_ B = 0;
         A_New = A_Hold - B_Hold;
      end
      else begin
         A_lessthan_B = 1;
         A_New = A_Hold;
      end
      //----------------------------------------------
      // Greatest common divisor found if B_Hold = 0
      //----------------------------------------------
      if (B_Hold == 0) begin
         Done = 1;
         Y = A_Hold;
      end
      else begin
         Done = 0;
         Y = 0;
      end
end
endmodule

 

Conclusions:

The reasons for the importance of being able to model hardware in both VHDL and Verilog has been discussed. VHDL and Verilog has been extensively compared and contrasted in a neutral manner.

Finite State Machine (FSM) Coding In Verilog

There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.

Verilog Code for FSM:
// 4-State Moore state machine
// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes.  (State
// transitions are synchronous.)
module seq_dect
(
    input    clk, data_in, reset,
    output reg  data_out
);
    // Declare state register
    reg        [2:0]state;
    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;

    // Determine the next state
    always @ (posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            case (state)
                S0:
                    if (data_in)
                        state <= S1;
                    else
                        state <= S0;
                S1:
                    if (data_in)
                        state <= S1;
                    else
                        state <= S2;
                S2:
                    if (data_in)
                        state <= S3;
                    else
                        state <= S2;
                S3:
                    if (data_in)
                        state <= S4;
                    else
                        state <= S2;
                S4:
                    if (data_in)
                        state <= S1;
                    else
                        state <= S2;
            endcase // case (state)
    end // always @ (posedge clk or posedge reset)
    // Output depends only on the state
    always @ (state) begin
        case (state)
            S0:
                data_out = 1'b0;
            S1:
                data_out = 1'b1;
            S2:
                data_out = 1'b0;
            S3:
                data_out = 1'b1;
            S4:
                data_out = 1'b1;               
            default:
                data_out = 1'b0;
        endcase // case (state)
    end // always @ (state)

endmodule // moore_mac

Finite State Machine (FSM) Coding In VHDL

There is a special Coding style for State Machines in VHDL as well as in Verilog.

Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.

 VHDL Code for FSM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Sequence detector for detecting the sequence "1011".
--Overlapping type.
entity seq_det is
port(   clk   : in std_logic;      --clock signal
        reset : in std_logic;      --reset signal
        S_in  : in std_logic;      --serial bit Input sequence   
        S_out : out std_logic);    -- Output        
end seq_det;
architecture Behavioral of seq_det is
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
begin
-- Synchronous Process
process(clk)
begin
    if( reset = '1' ) then                 --Synchronous Reset
        Current_State <= 'S0';
    elsif (clk'event and clk = '1') then   --Rising edge of Clock
        Current_State <= Next_State
    end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
    begin
        case Current_State is
            when S0 =>                     
                S_out <= '0';
                if ( s_in = '0' ) then
                    Next_State <= S0;
                else   
                    Next_State <= S1;
                end if;
            when S1 =>
                S_out <= '1';  
                if ( S_in = '0' ) then
                    Next_State <= S3;
                else   
                    Next_State <= S2;
                end if;
            when S2 =>
                S_out <= '0';  
                if ( S_in = '0' ) then
                    Next_State <= S0;
                else   
                    Next_State <= S3;
                end if;
            when S3 =>
                S_out <= '1';  
                if (S_in = '0' ) then
                    Next_State <= S2;
                else   
                    Next_State <= S4;
                end if;
            when S4 =>
                S_out <= '1';  
                if ( S_in = '0' ) then
                    Next_State <= S2;
                else   
                    Next_State <= S1;
                end if;
            when others =>
                NULL;
        end case;
    end if;
end process;   

Verilog Design With VHDL Testbench

// Two bit adder design in Verilog

module adder (a,b,carry,sum);
   //Port Declarations
   input [1:0] a;
   input [1:0] b;
   output [1:0] sum;
   output  carry;
   //Drivers for output signals
   reg [1:0]  sum;
   reg   carry;  
   // combination Logic for adder
   always @ (a or b) //Sensitive to inputs a or b
     begin
         {carry,sum} = a+b; 
     end
endmodule

 

--VHDL test bench for Verilog adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ADDER_TB is      --Top level entity dosen't have any port
end ADDER_TB;

architecture TB of ADDER_TB is

    component ADDER is
    port( A: in std_logic_vector(1 downto 0);
  B: in std_logic_vector(1 downto 0); 
  carry: out std_logic;     
  sum: out std_logic_vector(1 downto 0)
    );
    end component;

    signal A, B: std_logic_vector(1 downto 0);
    signal carry: std_logic;
    signal sum:  std_logic_vector(1 downto 0);

    begin
        DUT: ADDER port map (A, B, carry, sum);
    process  
variable err_cnt: integer :=0;
    begin -- Generating test vectors
-- case 1
A <= "00";      
B <= "00";
wait for 10 ns;
assert (sum="00") report "Sum Error!" severity error;
assert (carry='0') report "Carry Error!" severity error;
if (sum/="00" or carry/='0') then
     err_cnt:=err_cnt+1;
end if;
  -- case 2  
A <= "11";
B <= "11";
wait for 10 ns;  
assert (sum="10") report "Sum Error!" severity error; 
assert (carry='1') report "Carry Error!" severity error;
if (sum/="10" or carry/='1') then
     err_cnt:=err_cnt+1;
end if;
-- case 3
A <= "01";
B <= "10";
wait for 10 ns;  
assert (sum="11") report "Sum Error!" severity error; 
assert (carry='0') report "Carry Error!" severity error;
if (sum/="11" or carry/='0') then
     err_cnt:=err_cnt+1;
end if;
-- case 4
A <= "10";
B <= "01";
wait for 10 ns;   
assert (sum="11") report "Sum Error!" severity error; 
assert (carry='0') report "Carry Error!" severity error;
if (sum/="11" or carry/='0') then
     err_cnt:=err_cnt+1;
end if;
-- case 5
A <= "01";
B <= "01";
wait for 10 ns;
assert (sum="10") report "Sum Error!" severity error;
assert (carry='0') report "Carry Error!" severity error;
if (sum/="10" or carry/='0') then
     err_cnt:=err_cnt+1;
end if;
-- summary of testbench
if (err_cnt=0) then
     assert false
     report "Test completed successfully for adder!"
     severity note;
else
     assert true
     report "ERROR - Expected and received results are wrong"
     severity error;
end if;
wait;
    end process;
end TB;