VHDL Functions

I think all of the Designer wanted the Code simple and understandable. In simulation functions can be used to accomplish all kinds of things but For synthesis we must be more careful. Functions can be useful to model a component or a type conversion.

Warning, though!!! You must THINK HARDWARE!!!

Many functions have been defined in the IEEE libraries, e.g. rising_edge(CLK)

Function Properties :

• Function parameters can only be inputs.
• Functions can only return one value, specified by “return”.
• Statements inside the function are sequential except signal assignment and wait.
• No new signals can be declared, but variables can be.
• A function may declare local variables. These do not retain their values between successive calls, but are re-initialized each time.
• A function can be called as an expression, in either a concurrent or sequential statement
• Functions can be included either explicitly or through the use of packages.

Syntax:

function function_name (parameter_list) return type is
    declarations
begin
    sequential statements
end function_name;

Example:
entity full_add is
port(
         a, b, carry_in: in bit;
         sum, carry_out: out bit);
end full_add;

architecture full_add_arch of full_add is

function carry (a, b, c: in bit) return bit is
  begin
        return ((a and b) or (a and c) or (b and c));
end majority;

begin
       sum <= a xor b xor carry_in;
       carry_out <= carry(a, b, carry_in);
end full_add_arch;

VLSI Interview Questions - 2

• What is the frequency of the DDR / voltage
• What is the memory size ; explain prefetch in memory context
• What is the Bit length for data
• Basic protocol level DDR knowledge
• What is absolute jitter
• What are the types of jitter you know
• How do you make power measurements
• Asynchronous reset flip flop / Synchronous reset flip flop difference
• What is a asynchronous reset D flip flop
• How do you double the clock frequency using combinational logic
• What do you understand by synthesis
• What is the basic difference between ASIC and FPGA design flow
• Blocking and non-blocking statements
• Tools used for front end
• PCI clock frequency
• What is metastability
• Delay parameters which matter for DDR ( cas latency what do u know about it )
• RAS / CAS
• Master – Slave FF
• Add delay on FF1-FF2 D1Q-D2 path  and analyze a circuit ( a double inverter)
• Swap the delay onto the clock line and analyze the circuit ( double inverter )
• Delay nos. given 20 ns (double inverter) on clock skew line, 5 ns on the first FF to second FF line ; 100 ns clock period – analyze the circuit
• 4:1 mux from 2:1 mux ABCD in order – draw truth table and prove
• A equality comparator design – make it an inverter
• XOR gate from NAND gate
• Explain DDR protocol and timing
• Ethernet packet format
• Test setup and explain settings
• Two critical debug you have done in your career and lessons learnt
• Decoder design – explain address decoder how it works given x number of rows and columns draw timing and circuit
• 8085 block diagram ( general uP concepts)
• DRAM
• FF can be used in memory? Why / why not ?  FF vs DRAM
• Five skills obtained from board design / rules – best practices
• Latch vs FF
• VHDL code snippet
• SR FF.
• DDR banks
• 100 MHz clock is used to give input – need to send out data at 200 MHz suggest circuits for this
• DDR explanation – chip level
• 100 MHz in from 1 PLL clock / 100 MHz out from PLL2 clock – design circuit
• What problems will come in case (q 20 / 22)
• FIFO design details and problems
• some more design problems were asked to be analyzed
• What is set up time
• What is hold time
• ASIC Design flow
• Challenges in ASIC Design
• Latch and Flip-Flop
• Design a simple circuit for motion detector
• Use of a decoder
• Types of Flip Flop
• Which is the most common flip flop used in ASIC designs
• FF --- Combinational Logic --- FF ( Analysis of standard circuit)
• Analysis of circuit with delays ( buffers added to clock lines)
• How to find the maximum clock frequency of a given circuit
• Synthesis tools and styles
• Timing constraints to be given for ASIC design
• What happens when you decrease the clock frequency – does setup / hold time violations at say 300MHz frequency vanish at 3 MHz
• What all influence the delay of an element ( Flop – capacitance ?)
• What parameters influence delay ( temperature effect on delay)
• If input transition is faster what happens to delay of a cell
• What do you understand by drive strength
• High drive of a cell – correlates to what ?
• Importance of hold time (adder can become subtractor – Function change!!)
• How to solve set-up time violations
• How to solve hold time violations
• What is PRBS
• What is the difference between single ended and differential
• Why is PRBS needed in a tester
• USB protocol / packet level understanding? Basics explanation
• 80 MHz DDR – what do you understand from this
• SDR and DDR difference and advantages
• Test setup
• Triplexer – why passive optical networks what it means
• WDM – CO – CPE
• What do you understand by a Loopback why is it needed
• Challenges in finding maximum clock frequency in ASIC design
• Power estimation in chips ?
• Why is place and route important – any understanding of the same
• What is skew – clock skew
• What is slew – slew rate
• Why do you want to do verification and enter ASIC domain
• What is jitter
• What is cycle – cycle / period jitter. How is it estimated
• Common i/fs in a system
• Pulse width
• Why is setup and hold time first needed
• Effect of temperature on delays ( delay increases with temperature)
• Why clock skew arises
• What is positive and negative skew
• Is positive skew and advantage or disadvantage – how does it help
• What is the worst pattern that can be used to test a set of lines
• SSN – crosstalk
• what do you actually look for in SI
• What do you do in a bring-up
• What is Custom and Semi-Custom ASIC design
• ASIC – FPGA difference ( low power is a key)
• When a Flop is used; when a latch is used and why?
• Why random patterns?
• DFM?
• Clock tree routing problems
• Models for components
• Buffer circuit in IOs – Pulse width distortion / duty cycle distortion why it happens performance before and after pads causes for degradation
• Can you explain a general verification methodology flow 
• Explain your verification architecture 
• Why do you think we need functional coverage 
• Can you explain e-manager coverage implementation methods you have used 
• DDR + problems you faced in bring up 
• Can you give me an FSM/code/circuit to implemet code for following waveform 
• 32 bit addr / 32 bit data / size -- map to 64 bit memory - give structure / how will you sample data for byte, word, half word, dword accesses 
• You have 256 MB sys memory - (insufficient say for ur huge ASIC) how will u verify 
• Dynamic memory 
• List and indexed lists 
• Can you explain some RISC processor architecture you know 
• RISC vs CISC you know from college 
• How can specman handle semaphores 
• Some addressing fundamentals
• Multiple threads in your env - what did you implement to run three cores simultaneously. 
• AXI - addressing ; 4k page boundary cross over fetches; wrapping concept ; Multiple slave out of order transaction support - waveforms as to how these transactions will be ; size / length concepts

Silver jubilee of annual VLSI Design Conference in Hyderabad

The 25th International Conference on VLSI Design and the 11th International Conference on Embedded Systems is being held during January 7 – 11, 2012 at Hyderabad.

This year marks the silver jubilee of the VLSI Design Conference and therefore features an overview of the history of the conference by Vishwani D. Agarwal from Auburn University. The theme this year is Embedded solutions for emerging markets – consumer, energy and automotive.

Jaswinder Ahuja, of Cadence India, and President, VLSI Society of India, delivers the opening keynote on 'Semiconductor industry: Best of times, worst of times, and nowhere else would I rather be!'

Emerging Trends in Process Technologies by Jean Boufarhat of AMD and Samarjit Chakraborty of the Technical University of Munich, Germany, on Challenges in Automotive Cyber-physical Systems Design are two other lectures.

The conference, which features tutorials on 7-8, 2012, really gets going during January 9-11, 2012 and will also see a panel discussion on SoC Realization – A Bridge to New Horizons or a Bridge to Nowhere?

Among other attractions are Intel's Ravi Kuppuswamy on 15 billion by 2015 - Transformation of Embedded Devices to Intelligent Systems; Rajesh Gupta from the University of California San Diego on The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines; Berty Gyselinckx from IMEC, Belgium on A wireless sensor a day keeps the doctor away; Sri Parameswaran from the University of New South Wales on Security and Reliability in Embedded Systems and, Suresh Menon of Xilinx on the FPGA Roadmap: Technology Chalenges and Transitioning to Stacked Silicon Interconnect.

The guest lecture is to be delivered by Rajeev Madhavan, chairman and CEO, Magma Design Automation on The future of Semiconductor Design; What the Indian Electronics Industry can learn from Apple.

Meanwhile, The 3rd IEEE International Workshop on Realiability Aware System Design and Test is also being held at Hyderabad during 7-8, 2012 at Hyderabad, in conjunction with the VLSI Design Conference.

The glitch that stole the FPGA's energy efficiency

Field-programmable gate arrays (FPGAs) are notorious for high power consumption. They are hard to power down in the same way as custom logic - so they have considerable static power consumption - and they use a lot more gates to achieve the same job with their greater flexibility.

However, a good proportion of an FPGA's power consumption is avoidable. A 2007 study carried out by researchers at the University of British Columbia and published in IEEE Transactions on VLSI Systems found that up to three quarters of the dynamic power consumption could be ascribed to glitches rather than actual functional state transitions for some types of circuit.

The heart of the problem lies with timing: early-arriving signals can drive outputs to the wrong state before the situation is 'corrected' by later signals and before the final state is ready for sampling at the next clock transition. When you consider the large die size of FPGAs relative to custom logic, it is not hard to see why delays can be so large between signals.

UBC's Julien Lamoureux and colleagues recommended the use of delay elements to align signals in time to reduce these glitch events.

At the International Symposium on Low Power Electronic Design earlier this year, Warren Shum and Jason Anderson of the University of Toronto proposed an alternative: making use of the don't care conditions used in logic synthesis to also filter out potential glitches:

"This process is performed after placement and routing, using timing simulation data to guide the algorithm...Since the placement and routing are maintained, this optimization has zero cost in terms of area and delay, and can be executed after timing closure is completed."

The alterations are made in the LUTs iteratively to create new truth tables that will reduce the number of glitch transitions during operation, borrowing some concepts from asynchronous design where glitches are considered actively dangerous rather than inconvenient. On benchmark circuits, the technique reduced glitch power by around 14 per cent on average and up to half in some cases.

Intel 32nm Medfield mobile processor specs and benchmarks leaked

The popular chip maker Intel that I like to call chipzilla is preparing their own mobile processor or SoC (system on chip) called Medfield that we all have probably heard about a few times. They’ve shown off a prototype device too and more details on that are below. Today we have some leaked specs and benchmarks that are actually quite impressive that put this new Intel mobile processor right up there with NVIDIA’s Tegra 2 and Qualcomm’s dual-core chipsets. More competition the better right guys?

Intel may still be a ways off from launching Android smartphones and tablets but being fully supported by 4.0 Ice Cream Sandwich they are headed in the right direction — and now we have specs and performance ideas to help our minds wander with the possibilities. Apparently VR-Zone got all the info on Intel’s first true attempt at a full out SoC and we have all the details.

The 1.6 GHz x86 Intel mobile processor was running on a reference design 10″ tablet with 1GB of RAM, 16GB of storage, WiFi, Bluetooth, camera’s and all that other usual stuff, and was tossed up against the current big dogs like the Tegra 2. Apparently they ran a few Caffeinemark 3 benchmarks and the higher clocked Intel Atom scored around 10,500 while the Tegra 2 hit 7,500 and Qualcomm’s 1.5 GHz dual-core racked up around 8,000 points.

Currently the power consumption was higher than wanted or anticipated and that could cause a problem with battery life obviously. Intel plans to cut that down a bit and make some strides in efficiency not to mention be launching on Android 4.0 ICS devices later next year. I’m sure we’ll be seeing more than a few production units at CES 2012 so stay tuned as our entire team will be there live.

A processor company as huge as Intel running on a wide array of Android devices could be a game-changer if done right so we’ll continue to monitor and update as we hear more.

Intel’s Medfield-based Android Smartphone and Tablet

Intel is coming to mobile phones! Really! The chipmaker is gearing up to show off its Medfield processors at CES this year, which would be exciting if I hadn't heard this same tale way too many times before.

Intel is the company that cries wolf in mobile. Back in 2006, Intel made the mistake of ditching its Xscale line, the processors used in many early smartphones and successful PDAs. Under the questionable guidance of Marvell, Xscale then went from a dominant mobile brand to just one among many chip lines out there.

That left Intel with absolutely zero access to mobile devices. Ever since then, the company's been trying to get back into the game. But rather than enhance industry-standard ARM designs, Intel's been trying to sell everyone on x86-based chips.

Intel appears one step closer to finally breaking into the mobile arena after making their reference tablet and smartphone designs accessible to MITs Technology Review. Both devices are based around Intel’s Medfield iteration of their Atom processor, a chip based on the 32nm manufacturing process and promising better battery life than previous mobile CPUs from the silicon maker.

The Medfield-based reference smartphone was reportedly up to snuff with other currently available handset designs, boasting “Blu-ray0quality” video and the ability to shoot burst photos at 15 frames per second. The handset made available was running Android 2.3, but the tablet featured Android 4.0. Google and Intel have talked about working more closely with the development of the latest version of Android, and it could pay off as the reference tablet was said to be both as thing and as lightweight as the iPad 2 while outperforming the current generation of Android 3.0 slates.

Intel still has some work to do in integrating 3G and 4G components into the Medfield design, but the company looks to make a push over the next year or two to establish itself as a leader in the mobile market. Companies such as Qualcomm and NVIDIA currently have a leg up, but if Intel’s design proves as powerful as initial reports the battle could be starting to heat up.

Nobody's listened so far. Here are some highlights of Intel's failed push into mobile:

June 2006: Intel sells off Xscale, which had won a 2004 PCMag Technical Excellence award for heralding a new era of multimedia smartphones. Xscale was used in successful products like HP's iPAQs, Motorola's Q series, the Dell Axim and the Palm Treo. According to The Register, Intel wanted to push x86-based chips into smartphones rather than sticking with ARM designs. 

September 2007: At that year's Intel Developer Forum, Intel says it has two new chips designed for devices with 4-inch screens. Menlow and Moorestown make it into exactly zero popular handheld devices over the next few years. 

March 2008: Intel introduces the Atom processor, saying it will power "MIDs," or handheld, mobile Internet devices. Over the next year many companies introduce MIDs, but nobody buys any of them. Rather than being a power-guzzling mobile chipset, the Atom finds success in the netbook realm as a slow but power-efficient laptop chipset.

August 2008: Intel introduces the CE 3100, its first system-on-a-chip for consumer electronics. The CE 3100 generates several smart TV announcements but fewer actual sales of smart TVs.

February 2009: Intel brings a "MID bar" to Mobile World Congress. In Hebrew, "midbar" means "wilderness," as in "forty years wandering in the." Intel also announces an alliance with LG to produce more MIDs nobody wants.

January 2010: Intel says the second-generation Atom, called Moorestown, will be a real mobile chipset. Intel introduces the first phone based on the Atom Moorestown processor, the LG GW990. It is about the size and shape of a brick. It never appears in any large market. However, Intel keeps talking up Moorestown throughout 2010.

February 2010: Intel joins with Nokia to promote MeeGo, a new Linux-based OS that's the merger of Intel's Moblin and Nokia's Maemo. MeeGo is a stunning failure; Intel abandoned the project in September 2011.

January 2011: Intel CEO Paul Otellini says Windows 8 will run on smartphones with Intel chips. Other than one Steve Ballmer misquote last November, Microsoft has held a party line since then that Windows 8 will run on tablets and PCs, but not phones.

February 2011: MeeGo and Moorestown don't impress the market. Let's try again! Intel says its "Medfield" system-on-a-chip designs will come in 2012. Not much comes of Intel's mobile strategy in 2011 as the company gears up for Medfield, which will be shown at CES 2012.

March 2011: The head of Intel's ultra-mobile division leaves the company.

December 2011: Intel restructures its mobile division in an attempt to gain some traction.

To recap: fail, fail, fail, fail, fail. Faily fail fail.

Why Intel Might Succeed

There are a few new factors which might improve Intel's chances this time around. Back in September, Google said it would optimize Android for the next generation of Intel processors. That gives Intel a better OS than the proprietary Moblin/MeeGo nonsense it was working with before.

Windows 8 is also on the horizon, and while Windows 8 will work on ARM processors - a major threat to Intel - it means there will be a major tablet-oriented OS where the vast majority of legacy apps will be Intel-optimized. That could sway tablet developers to work with Intel chips.

In the phone world, though, the massive ecosystem around ARM means that Intel's sales pitch will have to be very compelling. The mobile-phone chip world is much more competitive than the desktop world Intel is used to. Within the ARM ecosystem alone, TI, Qualcomm, Nvidia, ST-Ericsson, Rockchip and others are constantly fighting for dominance. And mobile phone makers who want to try new architectures can also turn to MIPS or Power.

Intel has for years coasted on its critical mass in the PC industry. Even Apple came over to Intel after many years because of its low cost and economies of scale. But Intel doesn't have that advantage over companies like TI and Qualcomm in mobile.

It's not just about matching ARM-based designs on speed and power consumption, either. Intel will have to provide significantly better performance or lower power consumption to pull manufacturers away from the default, ARM world. Intel says it can do that by using a 32-nanometer process to produce its new system-on-a-chip. That's a solid argument, but Intel has made this argument too many times before. ARM vendors aren't far behind, either; both TI and Qualcomm have chips coming next year based on an even more efficient 28nm process.

We have to remember Michael Gartenberg's First Law. (Okay, maybe it's his second or third; not so sure of the numbering.) The dean of mobile tech analysts once told me, "never underestimate anyone very rich and very patient." That goes for Microsoft, and it goes for Intel as well.

Indian semiconductor company ships 12 million ICs

Bangalore, India based analog and mixed signal semiconductor chip design company; Cosmic Circuits has shipped 12 Million ICs till November 2011 and expects gross shipments of ASICs to exceed 16 Million ICs by March 2012. This is a good news for Indian ESDM industry, where an Indian company able to ship millions of chips.

Cosmic Circuits says its ICs are used in applications such as tablets, netbooks, cell phones and various other applications. Two main areas of focus are SensorASIC (analog companion chips for sensor applications) and PMASIC (custom power management solutions for portable electronics).

Ganapathy Subramaniam, the CEO of Cosmic Circuits, is projecting his company as one stop solution for all of their analog needs. Cosmic has 5 ICs in production now and expect to have nearly 10 ICs in production by 2012. Cosmic expect to ship more than 25M ICs in 2012 based on forecasts it has received from its customers.
India, where the demand for chips goes in billions both in revenue and shipment, needs Cosmic like companies to balance its trade deficit in electronics hardware.

Its time for VLSI design service companies in India to get into own product development.