Reset synchronizer

A day before there was a discussion about Synchronous and Asynchronous reset and Reset Synchronizer. I would like to share my views and some Ideas that I came to know.

Implementation of Synchronous and Asynchronous reset should depend on what you are looking at. There is a timing constraint on the rising edge of the reset ( assuming an active low reset) which can create one cycle uncertainty in the data being latched in by the FF. So for example if the start of a state machine depends on when the input FF gets the data and it doesn't matter if it starts one cycle early or late, there is no problem in using Asynchronous Reset. But if you have a high speed interface with say 6 bits of data being latched by the FF's and reset release happens very close to the clock edge then you have a serious problem that some Flops can get the data and some won't.

So it is really depended on what your design does on what kind of reset you should have. The safe methodology from my point of view is to use Asynch resets as long as the clock starts after the reset has been released.  Or to synchronize the Reset with the clock and make sure that the reset network delay including the CLK->Q delay of the synchronizing flop is less then the clock period - the worst removal timing of the FF's on the network.

 

VHDL Attributes

Formal Definition
A value, function, type, range, signal, or constant that may be associated with one or more named entities in a description.

Simplified Syntax
object'attribute_name

Description
Attributes allow retrieving information about named entities: types, objects, subprograms etc. VHDL standard defines a set of predefined attributes. Additionally, users can define new attributes, and then assign them to named entities by specifying the entity and the attribute values for it. See attributes (user-defined) for details.

Predefined attributes denote values, functions, types, and ranges that characterize various VHDL entities. Separate sets of attributes are predefined for types, array objects or their aliases, signals and named entities.

Each type or subtype T has a basic attribute called T'Base, which indicates the base type for type T (Table 1). It should be noted that this attribute could be used only as a prefix for other attributes.

Table 1. Attributes available for all types

Attribute	Result
T'Base	base type of T

Scalar types have attributes, which are described in the Table 2. Letter T indicates the scalar type.

Table 2. Scalar type attributes

Attribute	Result type	Result
T'Left	same as T	leftmost value of T
T'Right	same as T	rightmost value of T
T'Low	same as T	least value in T
T'High	same as T	greatest value in T
T'Ascending	boolean	true if T is an ascending range, false otherwise
T'Image(x)	string	a textual representation of the value x of type T
T'Value(s)	base type of T	value in T represented by the string s

Discrete or physical types and subtypes additionally have attributes, which are described in Table 3. The discrete or physical types are marked with letter T before their names.

Table 3. Attributes of discrete or physical types and subtypes

Attribute	Result type	Result
T'Pos(s)	universal integer	position number of s in T
T'Val(x)	base type of T	value at position x in T (x is integer)
T'Succ(s)	base type of T	value at position one greater than s in T
T'Pred(s)	base type of T	value at position one less than s in T
T'Leftof(s)	base type of T	value at position one to the left of s in T
T'Rightof(s)	base type of T	value at position one to the right of s in T

Array types or objects of the array types have attributes, which are listed in the Table .4. Aliases of the array type objects have the same attributes. Letter A denotes the array type or array objects below.

Table 4. Attributes of the array type or objects of the array type

Attribute	Result
A'Left(n)	leftmost value in index range of dimension n
A'Right(n)	rightmost value in index range of dimension n
A'Low(n)	lower bound of index range of dimension n
A'High(n)	upper bound of index range of dimension n
A'Range(n)	index range of dimension n
A'Reverse_range(n)	reversed index range of dimension n
A'Length (n)	number of values in the n-th index range
A'Ascending(n)	True if index range of dimension n is ascending, False otherwise

Signal attributes are listed in Table 5. Letter S indicates the signal names.

Table 5. Signals attributes

Attribute	Result
S'Delayed(t)	implicit signal, equivalent to signal S, but delayed t units of time
S'Stable(t)	implicit signal that has the value True when no event has occurred on S for t time units, False otherwise
S'Quiet(t)	implicit signal that has the value True when no transaction has occurred on S for t time units, False otherwise
S'Transaction	implicit signal of type Bit whose value is changed in each simulation cycle in which a transaction occurs on S (signal S becomes active)
S'Event	True if an event has occurred on S in the current simulation cycle, False otherwise
S'Active	True if a transaction has occurred on S in the current simulation cycle, False otherwise
S'Last_event	the amount of time since last event occurred on S, if no event has yet occurred it returns Time'High
S'Last_active	the amount of time since last transaction occurred on S, if no event has yet occurred it returns Time'High
S'Last_value	the previous value of S before last event occurred on it
S'Driving	True if the process is driving S or every element of a composite S, or False if the current value of the driver for S or any element of S in the process is determined by the null transaction
S'Driving_value	the current value of the driver for S in the process containing the assignment statement to S

The named entities have attributes described in Table 6. Letter E denotes the named entities.

Table 6. Attributes of named entities

Attribute	Result
E'Simple_name	a string representing the simple name, character literal or operator symbol defined in the declaration of the item E
E'Path_name	a string describing the path through the design hierarchy, from the root entity or package to the item E
E'Instance_name	a string describing the path through the design hierarchy, from the root entity or package to the item E, but including the names of the entity and architecture bound to each component instance in the path

Paths which can be written using E'Path_name and E'Instance_name are used for reporting and assertion statements. They allow specifying precisely where warnings or errors are generated. E'Simple_name attribute refers to all named entities, E'Path_name and E'Instance_name can refer to all named entities apart from the local ports and generic parameters in the component declaration.

There is one more predefined attribute: 'Foreign' that allows the user to transfer additional information to the simulator. The information contains the instruction for special treatment of a given named entity. The exact interpretation of this attribute, however, depends on its implementation in particular simulator.

 

Examples

Example 1

type Table is array (1 to 8) of Bit;
variable Array_1 : Table := "10001111";
Array_1'Left, the leftmost value in index range of Table array, is equal to 1.

Example 2

type Table is array (Positive range <>) of Bit;
subtype Table_New is Table (1 to 4);
Table_New'Base, the base type of the Table_New subtype is Table.

Example 3

type New_Range is range 1 to 10;
New_Range'Ascending is TRUE (the New_Range type is of ascending range).

Example 4

type New_Values is (Low, High, Middle);
New_Values'Pred(High) will bring the 'Low' value.

Example 5

type Table is array (1 to 8) of Bit;

Table'Range(1) is the range of the first index of Table type and returns '1 to 8'; Table'Range will have the same interpretation for one dimensional array.

 

Important Notes

• Not all predefined attributes are supported by synthesis tools; most tools support 'high, 'low, 'left, 'right, range, 'reverse_range, 'length and 'event. Some also support'last_value and 'stable.

VHDL Configuration

Used to bind component instances to design entities and collect architectures to make, typically, a simulatable test bench. One configuration could create a functional simulation while another configuration could create the complete detailed logic design. With an appropriate test bench the results of the two configurations can be compared.

Note that significant nesting depth can occur on hierarchal designs. There is a capability to bind various architectures with instances of components in the hierarchy. To avoid nesting depth use a configuration for each architecture level and a configuration of configurations. Most VHDL compilation/simulation systems allow the top level configuration name to be elaborated and simulated.

Syntax:
configuration identifier of entity_name is
     [ declarations , see allowed list below ]
     [ block configuration , see allowed list below ]
  end configuration identifier ; 

To understand configuration in depth let us consider below entity and architectures,

Entity E1 is
end E1;

Architecture A1 of E1 is
end Architecture A1;

Architecture A2 of E1 is
end Architecture A2;

Architecture A3 of E1 is
end Architecture A3;

Entity E2 is
end E2;

Architecture A1 of E2 is
   Component E1;
begin
   L1: E1 port map ();
   L2: E1 port map ();
end Architecture A1;

Architecture A2 of E2 is
begin
behavioural discription;
end Architecture A2;

Entity E3 is
end E3;

Architecture A1 of E3 is
   Component E1;
   Component E2;
begin
   L1: E1 port map ();
   L2: E2 port map ();
   L3: E2 port map ();
   L4: E1 port map ();
end Architecture A1;

Architecture A2 of E3 is
begin
behavioural discription;
end Architecture A2;

Below is the detailed configuration for entity E3;

Configuration C1 of E3 is
   for A1
        for L1 : E1
        use entity work.E1(A1);
        end for;

        for L2 : E2
        use entity work.E2(A2);
        end for;

        for L3 : E2
        use entity work.E2(A1);
             for A1
             use entity work.E1(A2);
             end for;
        end for;

        for L4 : E1
        use entity work.E1(A3);
        end for;
   end for;

end Configuration C1;

Shared Variable in VHDL

How to use a single variable in more than one process…!!

VHDL87 limited the scope of the variable to the process in which it was declared. Signals were the only means of communication between processes, but signal assignments require an advance in either delta time or simulation time.

VHDL '93 introduced shared variables which are available to more than one process. Like ordinary VHDL variables, their assignments take effect immediately. However, caution must be exercised when using shared variables because multiple processes making assignments to the same shared variable can lead to unpredictable behavior if the assignments are made concurrently. The VHDL ‘93 standard does not define the value of a shared variable it two or more processes make assignments in the same simulation cycle.

The syntax of the shared variable is similar to that of the normal variable. However, the keyword SHARED is placed in front of VARIABLE in the declaration

Example:

Architecture SV_example of example is
      shared variable status_signal : bit;
begin
     p1 : process (Clock,In1)
     begin
          if(status_signal) then
          ...
          end if;
          status_signal :='0';
     end process;

     p2 : process (Clock,In2)
     begin
          if(!(status_signal)) then
          ....
          end if;
          status_signal:='1';
     end process p2;

end SV_example;

Above example shows the use of shared variable in more than one process.

IBM developing storage device of just 12 atoms..!!!

If you're impressed with how much data can be stored on your portable hard drive, well ... that's nothing. Scientists have now created a functioning magnetic data storage unit that measures just 4 by 16 nanometers, uses 12 atoms per bit, and can store an entire byte (8 bits) on as little as 96 atoms - by contrast, a regular hard drive requires half a billion atoms for each byte. It was created by a team of scientists from IBM and the German Center for Free-Electron Laser Science (CFEL), which is a joint venture of the Deutsches Elektronen-Synchrotron DESY research center in Hamburg, the Max-Planck-Society and the University of Hamburg.

The storage unit was created one atom at a time, using a scanning tunneling microscope located at IBM's Almaden Research Center in San Jose, California. Iron atoms were arranged in rows of six, these rows then grouped into pairs, each pair capable of storing one bit of information - a byte would require eight pairs of rows.

Each pair can be set to one of two possible magnetic configurations, which serve as the equivalent of a 1 or 0. Using the tip of the microscope, the scientists were able to flip between those two configurations on each pair, by administering an electric pulse. They were subsequently able to "read" the configuration of each pair, by applying a weaker pulse using the same microscope.

While conventional hard drives utilize a type of magnetism known as ferromagnetism, the atom-scale device uses its opposite, antiferromagnetism. In antiferromagnetic material, the spins of neighboring atoms are oppositely aligned, which keeps them from magnetically interfering with one another. The upshot is that the paired rows of atoms were able to be packed just one nanometer apart from one another, which wouldn't otherwise have been possible.

Before you start expecting to find antiferromagnetic rows of atoms in your smartphone, however, a little work still needs to be done. Presently, the material must be kept at a temperature of 5 Kelvin, or -268ºC (-450ºF). The IBM/CFEL researchers are confident, however, that subsequent arrays of 200 atoms could be stable at room temperature.

It was found that 12 atoms was the minimum number that could be used for storing each bit, before quantum effects set in and distorted the information. "We have learned to control quantum effects through form and size of the iron atom rows," said CFEL's Sebastian Loth. "We can now use this ability to investigate how quantum mechanics kicks in. What separates quantum magnets from classical magnets? How does a magnet behave at the frontier between both worlds? These are exciting questions that soon could be answered."

IBM Research - Almaden physicist Andreas Heinrich explains the industry-wide need to examine the future of storage at the atomic scale and how he and his teammates started with 1 atom and a scanning tunneling microscope and eventually succeeded in storing one bit of magnetic information reliably in 12 atoms.

VHDL Procedures

The procedure is a form of subprograms. It contains local declarations and a sequence of statements. Procedure can be called in any place of the architecture. The procedure definition consists of two parts:

• The procedure declaration, which contains the procedure name and the parameter list required when the procedure is called;

• The procedure body, which consists of the local declarations and statements required to execute the procedure.

PROCEDURE DECLARATION

The procedure declaration consists of the procedure name and the formal parameter list.

In the procedure specification, the identifier and optional formal parameter list follow the reserved word procedure.

procedure Procedure_1 (variable X, Y: inout Real);

Objects classes constants, variables, signals, and files can be used as formal parameters. The class of each parameter is specified by the appropriate reserved word, unless the default class can be assumed (see below). In case of constants, variables and signals, the parameter mode determines the direction of the information flow and it decides which formal parameters can be read or written inside the procedure. Parameters of the file type have no mode assigned.

There are three modes available: in, out, and inout. When in mode is declared and object class is not defined, then by default it is assumed that the object is a constant. In case ofinout and out modes, the default class is variable. When a procedure is called, formal parameters are substituted by actual parameters. If a formal parameter is a constant, then actual parameter must be an expression. In case of formal parameters such as signal, variable and file, the actual parameters must be objects of the same class. Below example presents several procedure declarations with parameters of different classes and modes.

procedure Proc_1 (constant In1: in Integer; variable O1: out Integer);
procedure Proc_2 (signal Sig: inout Bit);

A procedure can be declared also without any parameters.

PROCEDURE BODY

Procedure body defines the procedure's algorithm composed of sequential statements. When the procedure is called it starts executing the sequence of statements declared inside the procedure body.

The procedure body consists of the subprogram declarative part After the reserved word is and the subprogram statement part placed between the reserved words begin and end. The key word procedure and the procedure name may optionally follow the end reserved word.

Declarations of a procedure are local to this declaration and can declare subprogram declarations, subprogram bodies, types, subtypes, constants, variables, files, aliases, attribute declarations, attribute specifications, use clauses, group templates and group declarations.

procedure Proc_3 (X,Y : inout Integer) is
  type Word_16 is range 0 to 65536;
  subtype Byte is Word_16 range 0 to 255;
  variable Vb1,Vb2,Vb3 : Real;
  constant Pi : Real :=3.14;

procedure Compute (variable V1, V2: Real) is
  begin
    -- subprogram_statement_part
  end procedure Compute;

begin
    -- subprogram_statement_part
end procedure Proc_3;

A procedure can contain any sequential statements (including wait statements). A wait statement, however, cannot be used in procedures which are called from a process with a sensitivity list or from within a function.

procedure Transcoder_1 (variable Value: inout bit_vector (0 to 7)) is
begin
  case Value is
    when "00000000" => Value:="01010101";
    when "01010101" => Value:="00000000";
    when others => Value:="11111111";
  end case;
end procedure Transcoder_1;

The procedure Transcoder_1 transforms the value of a single variable, which is therefore a bi-directional parameter.

procedure Comp_3(In1,R:in real; Step :in integer; W1,W2:out real) is
variable counter: Integer;
begin
  W1 := 1.43 * In1;
  W2 := 1.0;
  L1: for counter in 1 to Step loop
    W2 := W2 * W1;
    exit L1 when W2 > R;
  end loop L1;
  assert ( W2 < R )
    report "Out of range"
      severity Error;
end procedure Comp_3;

The Comp_3 procedure calculates two variables of mode out: W1 and W2, both of the REAL type. The parameters of mode in: In1 and R constants are of real type and Step of the integer type. The W2 variable is calculated inside the loop statement. When the value of W2 variable is greater than R, the execution of the loop statement is terminated and the error report appears.

PROCEDURE CALL

A procedure call is a sequential or concurrent statement, depending on where it is used. A sequential procedure call is executed whenever control reaches it, while a concurrent procedure call is activated whenever any of its parameters of in or inout mode changes its value.

All actual parameters in a procedure call must be of the same type as formal parameters they substitute.

OVERLOADED PROCEDURES

The overloaded procedures are procedures with the same name but with different number or different types of formal parameters. The actual parameters decide which overloaded procedure will be called.

procedure Calculate (W1,W2: in Real; signal Out1:inout Integer);
procedure Calculate (W1,W2: in Integer; signal Out1: inout Real);
-- calling of overloaded procedures:
Calculate(23.76, 1.632, Sign1);
Calculate(23, 826, Sign2);

The procedure Calculate is an overloaded procedure as the parameters can be of different types. Only when the procedure is called the simulator determines which version of the procedure should be used, depending on the actual parameters.

Properties of Procedures

• Synthesis tools usually support procedures as long as they do not contain the wait statements.
• The Procedure declaration is optional - procedure body can exist without it. If, however, a procedure declaration is used, then a procedure body must accompany it.

VHDL Functions and Procedures

Functions and procedures in VHDL, which are collectively known as subprograms, are directly analogous to functions and procedures in a high-level software programming language such as C or Pascal. A procedure is a subprogram that has an argument list consisting of inputs and outputs, and no return value. A function is a subprogram that has only inputs in its argument list, and has a return value.

Subprograms are useful for isolating commonly-used segments of VHDL source code. They can either be defined locally (within an architecture, for example), or they can be placed in a package and used globally throughout the design description or project.

Statements within a subprogram are sequential (like a process), regardless of where the subprogram is invoked. Subprograms can be invoked from within the concurrent area of an architecture or from within a sequential process or higher-level subprogram. They can also be invoked from within other subprograms.

Subprograms are very much like processes in VHDL. In fact, any statement that you can enter in a VHDL process can also be entered in a function or procedure, with the exception of a wait statement (since a subprogram executes once each time it is invoked and cannot be suspended while it is executing). It is therefore useful to think of subprograms as processes that (1) have been located outside the body of an architecture, and (2) operate only on their input and (in the case of procedures) their output parameters.

Nesting of functions and procedures is allowed to any level of complexity, and recursion is also supported in the language. (Of course, if you expect to generate actual hardware from your VHDL descriptions using synthesis tools, then you will need to avoid writing recursive functions and procedures, as such descriptions are not synthesizable).