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Showing posts with label Memory. Show all posts
Showing posts with label Memory. Show all posts

Wednesday, 6 March 2013

Facebook: Goodbye to DRAM and hello to McDipper

McDipper, a Facebook-built implementation of the popular memcached key-value store designed to run on flash memory rather than pricier DRAM.

Memcached, for the unfamiliar, is an open-source key-value store that caches frequently accessed data in memory so applications can access and serve it faster than if it were stored on hard disks. It’s a very popular component of many web applications stacks, including at Facebook where the company runs thousands of memcached servers to power its various applications.

But DRAM is expensive, especially when you get to Facebook’s scale, and not all applications deserve that kind of performance. So, according to a Facebook Engineering post on Wednesday, the company designed McDipper to handle “working sets that had very large footprints but moderate to low request rates. … Compared with memory, flash provides up to 20 times the capacity per server and still supports tens of thousands of operations per second.”

Facebook has deployed McDipper for a handful of these workloads, the blog states, and has “reduced the total number of deployed servers in some pools by as much as 90% while still delivering more than 90% of get responses with sub-millisecond latencies.” It has been part of Facebook’s photo infrastructure for about a year and serves 150 gigabits of data per second — or “about one library of congress (10 TB) every 10 minutes” — over Facebook’s content-delivery network.

563268_10151454322497200_149974633_n

This is the same logic that drove Facebook to undertake its cold storage engineering effort for even more infrequently accessed data, which aims to find a middle ground between the inefficiency and latency of hard disks and the high cost of flash storage. To meet that goal, the company is getting creative by considering everything from lower-performance flash to Blu-ray — pretty much anything but tape — VP of Engineering Jay Parikh told me in January.

Building a tool like McDipper is the just the tip of the iceberg, though, when it comes to managing the cost and efficiency of infrastructure at large web companies such as Facebook. On Tuesday, eBay released its Digital Service Efficiency report that lays out a methodology for assessing the effect that infrastructure (more than 52,000 servers in eBay’s case; Facebook has even more) has on larger corporate goals such as clean energy and the bottom line.

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Wednesday, 20 February 2013

Micron shrinks 128Gb NAND flash memory to 146-square mm

micron_enterprise_nand_flash Micron Technology on Thursday introduced the industry's smallest 128Gb NAND flash memory device made using 20nm process technology. The new 128Gb device stores three bits of information per cell (3bpc or triple level cell [TLC]), which makes it smaller and more cost-efficient. 

Measuring 146mm2, the new 128Gb TLC device is more than 25% smaller than the same capacity of Micron's 20nm multi-level-cell (MLC) NAND device. The 128Gb TLC device is targeted at the cost-competitive removable storage market (flash cards and USB drives), which is projected to consume 35% of total NAND gigabytes in calendar 2013.1 Micron is now sampling the 128Gb TLC NAND device with select customers; it will be in production in calendar Q2.

"This is the industry's smallest, highest-capacity NAND flash memory device – empowering a new class of consumer storage applications. Every day we learn of new and innovative use cases for flash storage, underpinning the excitement and opportunity for Micron. We are committed to enriching our portfolio of leading Flash storage solutions that serve our broad customer base," said Glen Hawk, vice president of Micron's NAND solutions group.

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Thursday, 14 February 2013

How and why DDR4 timing is important

DDR4-RAMJEDEC's DDR4 DRAM standard is compatible with 3DIC architectures and is capable of data transfer rates up to 3.2 gigatransfers per second, Kristin Lewotsky notes in this article. "We've got a broad  population of folks who really haven't had the time or the business need to learn about DDR4," says Perry Keller of Agilent Technologies. "What we hope to do is familiarize them with DDR4: What it is, why it exists, what it can bring to their products, and how to do something practical with it." EE Times

Wednesday, 30 January 2013

Rambus Introduces R+ LPDDR3 Memory Architecture Solution

Virtium-DDR3-VLP-SO-UDIMM2 Sunnyvale, California, United States - January 28, 2013   – Rambus Inc. the innovative technology solutions company that brings invention to market, today announced its first LPDDR3 offering targeted at the mobile industry. In the Rambus R+ solution set, the R+ LPDDR3 memory architecture is fully compatible with industry standards while providing improved power and performance. This allows customers to differentiate their products in a cost-effective manner with improved time-to-market. Further helping improve design and development cycles, the R+ LPDDR3 is also available with Rambus’ collaborative design and integration services.

The R+ LPDDR3 architecture includes both a controller and a DRAM interface and can reduce active memory system power by up to 25% and supports data rates of up to 3200 megabits per second (Mbps), which is double the performance of existing LPDDR3 technologies. These improvements to power efficiency and performance enable longer battery life and enhanced mobile device functionality for streaming HD video, gaming and data-intensive apps.

“Each generation of mobile devices demands even higher performance with lower power. The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior vice president and general manager of the Memory and Interface Division at Rambus. “Since this technology is a part of our R+ platform, beyond the improvements in power and performance, we’re also maintaining compatibility with today’s standards to ensure our customers have all the benefits of the Rambus’ superior technology with reduced adoption risk.”

The seed to the improved power and performance offered by the R+ LPDDR3 architecture is a low-swing implementation of the Rambus Near Ground Signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced IO power. The R+ LPDDR3 architecture is built from ground up to be backward compatible with LPDDR3 supporting same protocol, power states and existing package definitions and system environments.

Additional key features of the R+ LPDDR3 include:

  • 1600 to 3200Mbps data rates
  • Multi-modal support for LPDDR2, LPDDR3 and R+ LPDDR3
  • DFI 3.1 and JEDEC LPDDR3 standards compliant
  • Supports package-on-package and discrete packaging types
  • Includes LabStation™ software environment for bring-up, characterization, and validation in end-user application
  • Silicon proven design in GLOBALFOUNDRIES 28nm-SLP process

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Monday, 5 November 2012

Intel's 335 Series SSD reviewed

SSDs have come a long way since Intel released its first, the X25-M, a little more than four years ago. That drive was a revelation, but it wasn't universally faster than the mechanical hard drives of the era. The X25-M was also horrendously expensive; it cost nearly $600 yet offered just 80GB of capacity, which works out to about $7.50 per gigabyte.

My, how things have changed.

boxSolid-state drives gotten a lot faster in the last few years. They're already pushing up against the throughput ceiling of the 6Gbps Serial ATA interface, leaving mechanical hard drives in the dust. I can't remember the last time we saw an HDD score better than an SSD in one of our performance tests.

More importantly, SSDs have become a lot more affordable. Today, you can get 80GB by spending $100. The sweet spot in the market is the 240-256GB range, where SSDs can be had for around $200—less than a dollar per gigabyte. Rabid competition between drive makers deserves some credit for falling prices, particularly in recent years. Moore's Law is the real driving factor behind the trend, though. The X25-M's NAND chips were built using a 50-nm process, while the new Intel 335 Series uses flash fabricated on a much smaller 20-nm process.

Designed for enthusiasts and DIY system builders, the 335 Series is aimed squarely at the sweet spot in the market with a 240GB model priced at $184. That's just 77 cents per gig, a tenfold reduction in cost in just four years. The price is right, but what about the performance? We've run Intel's latest through our usual gauntlet of tests to see how it stacks up against the most popular SSDs around.

Die shrinkin'
Intel and Micron have been jointly manufacturing flash memory since 2006 under the name IM Flash Technologies. The pair started with 72-nm NAND flash before moving on to the 50-nm chips used in the X25-M. The next fabrication node was 34 nm, which produced the chips used in the second-generation X25-M and the Intel 510 Series. 25-nm NAND found its way into the third-gen X25-M, otherwise known as the 320 Series, in addition to the 330 and 520 Series. Now, the Intel 335 Series has become the first SSD to use IMFT's 20-nm MLC NAND.

Building NAND on finer fabrication nodes allows more transistors to be squeezed into the same unit area. In addition to accommodating more dies per wafer, this shrinkage can allow more capacity per die. The 34-nm NAND used in the Intel 510 Series offered 4GB per die, with each die measuring 172 mm². When IMFT moved to 25-nm production for the 320 Series, the per-die capacity doubled to 8GB, while the die size shrunk slightly to 167 mm².

flashchips Two 4GB 34-nm dies, one 8GB 25-nm die, and the new 8GB 20-nm die. Source: Intel

The Intel 335 Series' 20-nm NAND crams 8GB onto a die measuring just 118 mm². That's not the doubling of bit density we enjoyed in the last transition, but it still amounts to a 29% reduction in die size for the same capacity. Based on how those dies fit onto each wafer, Intel says 20-nm production increases the "gigabyte capacity" of its flash fabs by approximately 50%. IMFT has been mass-producing these chips since December of last year.

As NAND processes shrink, the individual cells holding 1s and 0s get closer together. Closer proximity can increase the interference between the cells, which can degrade both the performance and the endurance of the NAND. Intel's solution to this problem is a planar cell structure with a floating, high-k/metal gate stack. This advanced cell design is purportedly the first of its kind in the flash industry, and Intel claims it delivers performance and reliability comparable to IMFT's 25-nm NAND. Indeed, Intel's performance and endurance specifications for the 335 Series 240GB exactly match those of its 25-nm sibling in the 330 Series.

nand

Intel says the 335 Series 240GB can push sequential read and write speeds of 500 and 450MB/s, respectively. 4KB random read/write IOps are pegged at 42,000/52,000. Thanks to the lower power consumption of its 20-nm flash, the new drive should be able to hit those targets while consuming less power than its predecessor. The 335 Series is rated for power consumption of 275 mW at idle and 350 mW when active, less than half the 600/850 mW ratings of its 25-nm counterpart.

On the endurance front, Intel's new hotness can supposedly withstand 20GB of writes per day for three years, just like the 330 Series. As one might expect, the drive is covered by a three-year warranty. Intel reserves its five-year SSD warranties for the 320 and 520 Series, whose high-endurance NAND is cherry-picked off the standard 25-nm production line. I suspect it will take Intel some time to bin enough higher-grade, 20-nm NAND to fuel upgrades to those other models.

Our performance results will illustrate how the 335 Series compares up to those other Intel SSDs. Expect the 320 Series to be much slower due to its 3Gbps Serial ATA interface. That drive's Intel flash controller can trace its roots back to the original X25-M, so the design is a little long in the tooth. The 520 Series, however, has a 6Gbps interface and higher performance specifications than the 335 Series. The two are based on the same SandForce controller silicon, though.

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Intel’s 335 Series SSD

ssd-335-1 Intel has revved up its mainstream SSD line from the Series 330 to the Series 335, and the company sent over a 240GB model for evaluation (and 240GB is apparently the only capacity it is launching this series with). The new drives feature 20nm NAND flash memory, compared with the 25nm chips in the older series, but Intel continues to use an LSI/SandForce SF-2281 controller with custom Intel firmware. The company uses the same controller in its Series 330 and Series 520 drives.

But what may be of most interest to consumers is that the Series 335 is significantly cheaper per gigabyte: Intel expects this 240GB drive to cost about the same as a 180GB Series 330. And while the product was officially embargoed until 8:30 a.m. on October 29, we saw it listed for sale online the evening of October 28 at prices between $184 and $225, including shipping.

Like its most recent predecessors, the Series 335 is outfitted with a SATA revision 3.0 (6gbits/s) interface, and the drive comes housed inside a 2.5-inch enclosure that is 9.5mm thick. That thick profile renders it unsuitable for many current ultraportables; however, the stout of heart can easily remove the board from its enclosure and fit it inside a thinner case or install it directly into a vacant drive bay (although doing either will likely void Intel’s three-year warranty).

Here are some results of 10GB copy and read tests. Keeping in mind that our current test bed uses a 7200-rpm hard drive to feed and read data from our test subjects, the 335 performed very well. It wrote our 10GB mix of files and folders at 93.2MBps and read them at 57.9MBps; and it wrote our single 10GB file at 124.1MBps while reading it at 129.8MBps.

 

Intel 335 Series SSD Features and Specifications:

  • CAPACITY: 240GB
  • COMPONENTS:
    • Intel 20nm NAND Flash Memory
    • Multi-Level Cell (MLC)
  • FORM FACTOR: 2.4-inch
  • THICKNESS: 9.5mm
  • WEIGHT: Up to 78 grams
  • SATA 6Gbps BANDWIDTH PERFORMANCE (IOM QD32):
    • SUSTAINED SEQ READ: 500 MB/s
    • SUSTAINED SEQ WRITE: 450 MB/s
  • READ & WRITE IOPS (IOM QD32):
    • RANDOM 4KB READS: Up to 42,000 IOPS
    • RANDOM 4KB WRITES: Up to 52,000 IOPS
  • COMPATIBILITY:
    • Intel SSD Toolbox w/SSD Optimizer
    • Intel Data Migration Software
    • Intel Rapid Storage Technology
    • Intel 6 Series Express Chipsets (w/ SATA 6Gpbs)
    • SATA Revision 3.0
    • ACS-2 (ATA/ATAPI Command Set 2)
    • Limited SMART ATA Feature Set
    • Native Command Queuing (NCQ) Command Set
    • Data Set Management Command Trim Attribute
  • POWER MANAGEMENT:
    • 5 V SATA Supply Rail
    • SATA Link Power Management (LPM)
  • POWER:
    • Active (MobileMark 2007 Workload: 350 mW (TYP)
    • Idle: 275 mW (TYP)
  • TEMPERATURE:
    • Operating: 0°C to 70°C
    • Non-Operating: -55°C to 95°C
  • CERTIFICATIONS & DECLARATION:
    • UL
    • CE
    • C-Tick
    • BSMI
    • KCC
    • Microsoft WHQL
    • VCCI
    • SATA-IO
  • PRODUCT ECOLOGICAL COMPLIANCE:
    • RoHS

 

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Tuesday, 25 September 2012

DesignWare DDR4 Memory Interface IP from Synopsys

Highlights:

  • Synopsys expands its industry-leading DesignWare® DDR Memory Interface IP family to include support for DDR4 SDRAMs
  • Backward compatibility with DDR3 and LPDDR2/3 mobile SDRAMs gives SoC designers flexibility as they transition from one SDRAM standard to the next
  • New DDR4 IP offers more features with up to 50 percent lower latency than the previous generation
  • DDR4 memory controller and PHY are connected by a standard DFI 3.1 interface to streamline connections to custom PHYs and controllers

Synopsys, Inc. (SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the emerging DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.

"Synopsys' support for DDR4 memory is an important contribution to building a robust DDR4 ecosystem," said Robert Feurle, vice president of DRAM marketing for Micron Technology, Inc. "DDR4 brings substantial power and performance benefits to the industry, and Micron is aggressively driving its introduction. By implementing their DesignWare DDR Interface IP with backward compatibility in mind, Synopsys is enabling chip developers to bridge the transition from today's DDR3-based SoCs to the upcoming DDR4 designs."

Synopsys' DesignWare DDR4 IP solution consists of the DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface. The new DDR4 IP supports all key DDR4 features planned for the upcoming JEDEC standard and, compared to the previous version, includes a 13 percent increase in raw bandwidth, up to a 50 percent reduction in overall latency and new low-power features that provide intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns. Real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance and minimizing latency.

"While the initial target markets for DDR4 are networking, server, and compute platforms, engineers designing for digital TVs, set-top-boxes, multi-function printing, smartphone and tablet applications will also adopt DDR4 DRAM as prices drop and performance improves," said Desi Rhoden, executive vice president, Montage Technology, and JEDEC memory chairman. "Synopsys has leveraged their participation at JEDEC to develop DDR4-compatible products before the actual standard has been released, which is a key benefit of JEDEC membership."

"Synopsys' complete DDR interface IP portfolio includes support for LPDDR, LPDDR2, LPDDR3, DDR, DDR2, and DDR3," said John Koeter, vice president of marketing for IP and systems at Synopsys. "With this announcement, we are broadening our portfolio to include support for DDR4 while maintaining backward compatibility with existing JEDEC standard SDRAMs. As new DDR standards evolve, designers look for reliable solutions. Synopsys' track record of over 320 DDR IP design wins demonstrates that we offer a low-risk path to silicon success."

Availability for the DesignWare DDR4 multiPHY and uMCTL2 with support for DDR4 is planned for Q4 2012.

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Saturday, 14 January 2012

IBM developing storage device of just 12 atoms..!!!

If you're impressed with how much data can be stored on your portable hard drive, well ... that's nothing. Scientists have now created a functioning magnetic data storage unit that measures just 4 by 16 nanometers, uses 12 atoms per bit, and can store an entire byte (8 bits) on as little as 96 atoms - by contrast, a regular hard drive requires half a billion atoms for each byte. It was created by a team of scientists from IBM and the German Center for Free-Electron Laser Science (CFEL), which is a joint venture of the Deutsches Elektronen-Synchrotron DESY research center in Hamburg, the Max-Planck-Society and the University of Hamburg.

The storage unit was created one atom at a time, using a scanning tunneling microscope located at IBM's Almaden Research Center in San Jose, California. Iron atoms were arranged in rows of six, these rows then grouped into pairs, each pair capable of storing one bit of information - a byte would require eight pairs of rows.

Each pair can be set to one of two possible magnetic configurations, which serve as the equivalent of a 1 or 0. Using the tip of the microscope, the scientists were able to flip between those two configurations on each pair, by administering an electric pulse. They were subsequently able to "read" the configuration of each pair, by applying a weaker pulse using the same microscope.

While conventional hard drives utilize a type of magnetism known as ferromagnetism, the atom-scale device uses its opposite, antiferromagnetism. In antiferromagnetic material, the spins of neighboring atoms are oppositely aligned, which keeps them from magnetically interfering with one another. The upshot is that the paired rows of atoms were able to be packed just one nanometer apart from one another, which wouldn't otherwise have been possible.

Before you start expecting to find antiferromagnetic rows of atoms in your smartphone, however, a little work still needs to be done. Presently, the material must be kept at a temperature of 5 Kelvin, or -268ºC (-450ºF). The IBM/CFEL researchers are confident, however, that subsequent arrays of 200 atoms could be stable at room temperature.

It was found that 12 atoms was the minimum number that could be used for storing each bit, before quantum effects set in and distorted the information. "We have learned to control quantum effects through form and size of the iron atom rows," said CFEL's Sebastian Loth. "We can now use this ability to investigate how quantum mechanics kicks in. What separates quantum magnets from classical magnets? How does a magnet behave at the frontier between both worlds? These are exciting questions that soon could be answered."

IBM Research - Almaden physicist Andreas Heinrich explains the industry-wide need to examine the future of storage at the atomic scale and how he and his teammates started with 1 atom and a scanning tunneling microscope and eventually succeeded in storing one bit of magnetic information reliably in 12 atoms.