ZeroN project, Computer-controlled magic levitation created by MIT student

What if materials could defy gravity, so that we could leave them suspended in mid-air?

MIT genius Jinha Lee has created an incredible computer-controlled system for levitating objects.

The project, called ZeroN, uses magnets, a Kinect visual system, plus special software that enables either the computer to move a steel ball around in space, or a human to just grab it and move it, essentially telling the computer where it should go.

ZeroN is a new physical/digital interaction element that can be levitated and moved freely by computer in a three dimensional space. Both the computer and people can move the ZeroN simultaneously. In doing so, people and computers can physically interact with one another in 3D space.

It can even remember how it was moved, then repeat the movement automatically.

I really want to experience it live …!!

http://www.leejinha.com/zeron

http://web.media.mit.edu/~jinhalee/zeron_jinha_lee.pdf

Xilinx introduces Vivado Design Suite

Xilinx Inc. has announced the Vivado Design Suite. It enables an IP and system centric next generation design environment. Especially meant for the next decade of ‘All-Programmable’ devices, it also accelerates the integration and implementation up to 4X. And, why now? That’s because the all-programmable devices enable programmable systems ‘integration.

There are system integration bottlenecks, such as design and IP re-use, integrating algorithmic and RTL level IP, mixing DSP, embedded, connectivity and logic, and verification of blocks and “systems”.
There are implementation bottlenecks as well, such as hierarchical chip planning, multi-domain and multi-die physical optimization, predictable ‘design’ vs. ‘timing’ closure, and late ECOs and rippling effect of changes.
Vivado accelerates productivity up to 4X. The design suite elements include an integrated design environment, has a shared scalable data model, is scalable to 100 million gates, and debug and analysis. It shares design information between implementation steps that ensures fast convergence and timing closure. This enables highly efficient memory utilization. Also, it is scalable to future families, that are greater than 10 million logic cells (100 million gates) and enables cross-probing across the entire design.
Vivado also enables packaging designs into system-level IP for re-use. You can share IP within your team, project or company. Any 3rd party IP is delivered with a common look and feel. You can re-use IP at any point in the implementation process. The IP can be source, placed, or placed and routed.

Tips for an Error-free Functional Simulation

Getting a VHDL code to work in the functional simulation is not always an easy task.This article will cover some tips to quickly point out the errors in the code and make your life easier.

1. Create a proper sensitivity list. Some times you may have to add other control signals too(other than clock) into you sensitivity list to get is working.
2. Initialize the signals and variables correctly. If they are not initialized(normally they are set to '0'), then these signals will appear as "U"in the simulation waveform.
3. If you see "X" in the waveform then that indicates concurrent writing to the same signal. A simple re-arrangement of the signal inside the process will normally take out this bug.
4. In case you have arrays in the design make sure to check for out of bound error. This happens when you read or write a different index than the one available within the range of array.
5. If elsif's are error prone. Always try to consider all the conditions of If elsif. If a particular condition is not considered then the value will remain unchanged. If you don’t want this to happen then make sure you reset the signal, using an else condition.
6. Within a process, signal assignments can be written in any order. They will get executed concurrently. But for variables, the order matters. line 1 is executed first, line 2 second and so on...
7. One way to debug the code is to force one or more signals as constants and test the design. This will help you in localizing the error.
8. Writing a location in RAM requires a small time delay. Account for this, while reading and writing from the same location in the same clock cycle. The read data will be the one written in the last clock cycle.
9. Try synthesizing the design. The synthesizer tool may give out some warnings or errors which will point you in the correct direction to solve the error in the functional simulation.
10. When using components in the design, use name instantiation, so that you don't accidentally assign wrong signals to the component ports.

VHDL to Verilog to VHDL Code Converter Tools & Tips

Most modern EDA tools will accept both VHDL and Verilog, and even combination of the two in the same design. Even though engineers try to convert from VHDL to Verilog, or Verilog to VHDL in some cases depends on their requirement in design work flow.

Possible Reasons of Code Conversion Between VHDL and Verilog

• To reuse existing designs
• To maintain both version of a design. Verilog for commercial, industrial purposes and VHDL for DoD requirements.
• To design, support the code for different countries like US, Europe and or Asia where preference for particular language differs.

As a general rule, it is better to write own coding in the targeted HDL such as VHDL or Verilog. However, the time you will spend on the “manual translation” could also be used to make a design on your own.

The commercially available code conversion/translation tools convert the code as module wise, and may not necessarily support every possible construct you can find in VHDL or Verilog.

In case of urgent need, the tools will help in translating the larger code from VHDL to Verilog (and Verilog to VHDL too) on the fly. Few of them are for command line use in UNIX environment, and a few are GUI enabled so that you can execute them in Windows.

VHDL to Verilog (Verilog to VHDL) Code Conversion Translation Tools

Here is the list of some popular Vendors, supply HDL code conversion tools. Few are free download, and others cost a little but gives a demo version with some limitation on code size.

• Synapticad’s V2V Translation Tool, supports both VHDL to Verilog and vice versa
• MyHDL, supports both VHDL to Verilog and vice versa
• TauDelta’s Verilog to VHDL RTL converter
• Trilent Networks HDL Translator
• Alternate System Concepts Inc.
• Avanti Corp.
• Aldec Corporation’s Active-HDL
• X-Tek Corporation’s XHDL
• FTL Systems
• Ocean Logic

Teach SystemVerilog Yourself

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.

While Think Verification focuses on the advanced stuff (check out our VMM Hacker's Guide series), there are many websites and blogs out there that offer free tutorials that can help you learn the basics of SystemVerilog.

Though we are going to cover all aspects of SystemVerilog in this site, We like to share with you some of the online available resources that you can refer. Here are a few links that will help you get started very quickly:

ASIC WORLD

A comprehensive tutorial that shows you most of the constructs and elements of the language. There's far more information than you need to get you through your first steps, but it's a good place to keep as reference. The examples given there also include snapshots from the simulator's output which is cool. Methodology is not covered there, although the author intends to cover that in the future.

DOULOS

Probably the first place to look. Doulos offers a sleek tutorial covering some of the most important elements of SystemVerilog in a nutshell. Although not comprehensive, we think their tutorial gives a nice overview of the language fundamentals that you should get familiar with, especially if you have experience in other HVLs. Their quick tutorial on Classes and Randomization will get you started rapidly.

ELECTRO-SOFTS

This tutorial covers the basic constructs of SystemVerilog quite thoroughly, along with some good examples. This might be a good place to go once you nail the basic concepts of the language. Methodology is not covered here but we liked their SVA (System Verilog Assertions) section.

TESTBENCH.IN

A comprehensive tutorial that covers all of SystemVerilog's fundamentals, including OOP and DPI. They also cover VMM quite well. There are a couple of labs for you to download if you're up for it. Overall - a great tutorial that teaches language as well as methodology.

SPECMAN-VERIFICATION

An evolving (and funny) tutorial on SystemVerilog that's quite different from the other "serious" looking tutorials out there. Avidan (the author) shares with us not only the basic constructs of SV but also his philosophical view on each one of them. Definitely worth a visit if you're into learning SystemVerilog. 

The 3 M's of Verification: Methodology! Methodology! Methodology!

SystemVerilog alone is not enough if you're serious about building verification environments. That's where standard methodology comes in. Today there are two main methodologies in the market for SystemVerilog. The first is VMM, the other is OVM. Both methodologies can do the job and there's plenty of information out there on each one of them. OVM-World and VMM-Central are probably the best places to start looking (pretty soon a new methodology is going to conquer the world - UVM, which is based on OVM plus parts of VMM). A word of advice - pay as much attention to methodology as you would to language constructs and syntax. In HVLs, and in SystemVerilog in particular, methodology accounts for the greater part of your verification project.

Draw NAND gate using 2:1 MULTIPLEXER

Design 1:

Design 2:

Draw XNOR gate using 2:1 MULTIPLEXER

Design 1:

Design 2: