IC Package Types :)

The semiconductor industry manufactures a very huge variety of integrated circuits that have different packaging requirements.  Package attributes that are taken into consideration when choosing a package type for a particular semiconductor device include: size, lead count, power dissipation, field operating conditions, and of course, cost.

Popular IC package types used in the semiconductor industry today are presented below.

Types of IC Packages (not shown in scale)

CBGA - Ceramic Ball Grid Array

CCGA - Ceramic Column Grid Array

CerDIP - Ceramic Dual-in-Line Package

CerPack - Ceramic Package

CLCC - Ceramic Leadless Chip Carrier

CPGA - Ceramic Pin Grid Array

CQFP - Ceramic Quad Flat Pack

D2PAK or DDPAK - Dou-ble Decawatt Package

D3PAK - Decawatt Package 3

DFN - Dual Flat No Leads Package

DPAK - Decawatt Package

FBGA - Fine-Pitch Ball Grid Array

JLCC - J-Leaded Ceramic Chip Carrier

LFBGA - Low Profile Fine-Pitch Ball Grid Array

LGA - Land Grid Array

LQFP - Low-Profile Quad Flat Package

MLP - Micro Leadframe Package

MQFP - Metric Quad Flat Package

MSOP - Micro Small Outline Package

PBGA - Plastic Ball Grid Array

PDIP - Plastic Dual-in-Line Package

PLCC - Plastic Leaded Chip Carrier

PPGA - Plastic Pin Grid Array

PQFN - Power Quad Flat No Leads Package

PQFP - Plastic Quad Flat Pack

PSOP - Power Small Outline Package

QFN - Quad Flat No Leads Package

QSOP - Quarter Size Outline Package

SBDIP - Sidebraze Dual-in-Line Package

SC-70 - Small Outline Transistor

SIP - Single-In-Line Package

SOIC - Small Outline IC Package

SOJ - Small Outline J-Lead Package

SOT-23 - Small Outline Transistor

SPDIP - Shrink Plastic Dual-in-Line Package

SSOP - Shrink Small Outline Package

TDFN - Thin Dual Flat No Leads Package

TFBGA - Thin Fine-Pitch Ball Grid Array

TQFN - Thin Quad Flat No Leads Package

TQFP - Thin Quad Flat Pack

TSOP - Thin Small Outline Package

TSSOP - Thin Shrink Small Outline Package

UTDFN - Ultra Thin Dual Flat No Leads Package

UTQFN - Ultra Thin Quad Flat No Leads Package

VFBGA - Very Thin Fine-Pitch Ball Grid Array

VSOP - Very Small Outline Package

XDFN - Extreme Thin Dual Flat No Leads Package

XQFN - Extreme Thin Quad Flat No Leads Package

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Rambus Introduces R+ LPDDR3 Memory Architecture Solution

Sunnyvale, California, United States - January 28, 2013   – Rambus Inc. the innovative technology solutions company that brings invention to market, today announced its first LPDDR3 offering targeted at the mobile industry. In the Rambus R+ solution set, the R+ LPDDR3 memory architecture is fully compatible with industry standards while providing improved power and performance. This allows customers to differentiate their products in a cost-effective manner with improved time-to-market. Further helping improve design and development cycles, the R+ LPDDR3 is also available with Rambus’ collaborative design and integration services.

The R+ LPDDR3 architecture includes both a controller and a DRAM interface and can reduce active memory system power by up to 25% and supports data rates of up to 3200 megabits per second (Mbps), which is double the performance of existing LPDDR3 technologies. These improvements to power efficiency and performance enable longer battery life and enhanced mobile device functionality for streaming HD video, gaming and data-intensive apps.

“Each generation of mobile devices demands even higher performance with lower power. The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior vice president and general manager of the Memory and Interface Division at Rambus. “Since this technology is a part of our R+ platform, beyond the improvements in power and performance, we’re also maintaining compatibility with today’s standards to ensure our customers have all the benefits of the Rambus’ superior technology with reduced adoption risk.”

The seed to the improved power and performance offered by the R+ LPDDR3 architecture is a low-swing implementation of the Rambus Near Ground Signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced IO power. The R+ LPDDR3 architecture is built from ground up to be backward compatible with LPDDR3 supporting same protocol, power states and existing package definitions and system environments.

Additional key features of the R+ LPDDR3 include:

• 1600 to 3200Mbps data rates
• Multi-modal support for LPDDR2, LPDDR3 and R+ LPDDR3
• DFI 3.1 and JEDEC LPDDR3 standards compliant
• Supports package-on-package and discrete packaging types
• Includes LabStation™ software environment for bring-up, characterization, and validation in end-user application
• Silicon proven design in GLOBALFOUNDRIES 28nm-SLP process

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