Facebook: Goodbye to DRAM and hello to McDipper

McDipper, a Facebook-built implementation of the popular memcached key-value store designed to run on flash memory rather than pricier DRAM.

Memcached, for the unfamiliar, is an open-source key-value store that caches frequently accessed data in memory so applications can access and serve it faster than if it were stored on hard disks. It’s a very popular component of many web applications stacks, including at Facebook where the company runs thousands of memcached servers to power its various applications.

But DRAM is expensive, especially when you get to Facebook’s scale, and not all applications deserve that kind of performance. So, according to a Facebook Engineering post on Wednesday, the company designed McDipper to handle “working sets that had very large footprints but moderate to low request rates. … Compared with memory, flash provides up to 20 times the capacity per server and still supports tens of thousands of operations per second.”

Facebook has deployed McDipper for a handful of these workloads, the blog states, and has “reduced the total number of deployed servers in some pools by as much as 90% while still delivering more than 90% of get responses with sub-millisecond latencies.” It has been part of Facebook’s photo infrastructure for about a year and serves 150 gigabits of data per second — or “about one library of congress (10 TB) every 10 minutes” — over Facebook’s content-delivery network.

This is the same logic that drove Facebook to undertake its cold storage engineering effort for even more infrequently accessed data, which aims to find a middle ground between the inefficiency and latency of hard disks and the high cost of flash storage. To meet that goal, the company is getting creative by considering everything from lower-performance flash to Blu-ray — pretty much anything but tape — VP of Engineering Jay Parikh told me in January.

Building a tool like McDipper is the just the tip of the iceberg, though, when it comes to managing the cost and efficiency of infrastructure at large web companies such as Facebook. On Tuesday, eBay released its Digital Service Efficiency report that lays out a methodology for assessing the effect that infrastructure (more than 52,000 servers in eBay’s case; Facebook has even more) has on larger corporate goals such as clean energy and the bottom line.

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Micron shrinks 128Gb NAND flash memory to 146-square mm

Micron Technology on Thursday introduced the industry's smallest 128Gb NAND flash memory device made using 20nm process technology. The new 128Gb device stores three bits of information per cell (3bpc or triple level cell [TLC]), which makes it smaller and more cost-efficient. 

Measuring 146mm², the new 128Gb TLC device is more than 25% smaller than the same capacity of Micron's 20nm multi-level-cell (MLC) NAND device. The 128Gb TLC device is targeted at the cost-competitive removable storage market (flash cards and USB drives), which is projected to consume 35% of total NAND gigabytes in calendar 2013.1 Micron is now sampling the 128Gb TLC NAND device with select customers; it will be in production in calendar Q2.

"This is the industry's smallest, highest-capacity NAND flash memory device – empowering a new class of consumer storage applications. Every day we learn of new and innovative use cases for flash storage, underpinning the excitement and opportunity for Micron. We are committed to enriching our portfolio of leading Flash storage solutions that serve our broad customer base," said Glen Hawk, vice president of Micron's NAND solutions group.

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How and why DDR4 timing is important

JEDEC's DDR4 DRAM standard is compatible with 3DIC architectures and is capable of data transfer rates up to 3.2 gigatransfers per second, Kristin Lewotsky notes in this article. "We've got a broad  population of folks who really haven't had the time or the business need to learn about DDR4," says Perry Keller of Agilent Technologies. "What we hope to do is familiarize them with DDR4: What it is, why it exists, what it can bring to their products, and how to do something practical with it." EE Times

Rambus Introduces R+ LPDDR3 Memory Architecture Solution

Sunnyvale, California, United States - January 28, 2013   – Rambus Inc. the innovative technology solutions company that brings invention to market, today announced its first LPDDR3 offering targeted at the mobile industry. In the Rambus R+ solution set, the R+ LPDDR3 memory architecture is fully compatible with industry standards while providing improved power and performance. This allows customers to differentiate their products in a cost-effective manner with improved time-to-market. Further helping improve design and development cycles, the R+ LPDDR3 is also available with Rambus’ collaborative design and integration services.

The R+ LPDDR3 architecture includes both a controller and a DRAM interface and can reduce active memory system power by up to 25% and supports data rates of up to 3200 megabits per second (Mbps), which is double the performance of existing LPDDR3 technologies. These improvements to power efficiency and performance enable longer battery life and enhanced mobile device functionality for streaming HD video, gaming and data-intensive apps.

“Each generation of mobile devices demands even higher performance with lower power. The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior vice president and general manager of the Memory and Interface Division at Rambus. “Since this technology is a part of our R+ platform, beyond the improvements in power and performance, we’re also maintaining compatibility with today’s standards to ensure our customers have all the benefits of the Rambus’ superior technology with reduced adoption risk.”

The seed to the improved power and performance offered by the R+ LPDDR3 architecture is a low-swing implementation of the Rambus Near Ground Signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced IO power. The R+ LPDDR3 architecture is built from ground up to be backward compatible with LPDDR3 supporting same protocol, power states and existing package definitions and system environments.

Additional key features of the R+ LPDDR3 include:

• 1600 to 3200Mbps data rates
• Multi-modal support for LPDDR2, LPDDR3 and R+ LPDDR3
• DFI 3.1 and JEDEC LPDDR3 standards compliant
• Supports package-on-package and discrete packaging types
• Includes LabStation™ software environment for bring-up, characterization, and validation in end-user application
• Silicon proven design in GLOBALFOUNDRIES 28nm-SLP process

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DDR4 SDRAM Standards published by JEDEC

The PC industry hasn't seen an updated memory spec in a while, and it was long past due. That upgrade came last week, as the memory standards group JEDEC revealed that it had published a spec for DDR4 SDRAM, defining "features, functionalities, AC and DC characteristics, packages and ball/signal assignments," that builds on the DDR3 spec, first published in 2007. The DDR4 spec applies to SDRAM devices from 2 GB through 16 GB for x4, x8 and x16 buses. Here's a look at some of the particulars.

“The new standard will enable next generation systems to achieve greater performance, significantly increased packaging density and improved reliability, with lower power consumption,” Macri said.

Double Data Rate

First and foremost, DDR4 memory doubles the maximum transfer rate of DDR3. The new spec supports a per-pin data rate of up to 3.2 giga transfers per second (GT/s), twice that of its predecessor's eventual maximum of 1.6 GT/s (the ceiling was raised over time). And, DDR4's max could likewise go higher, as necessary, to accommodate faster components and bus speeds. So far, the only processor roadmap we've seen in support of DDR4 has been Intel's, with its Haswell server processor slated for 2014; consumer-platform support isn't expected until sometime in 2015.

Meanwhile, JEDEC member company Samsung announced in July that it had begun sampling the "industry's first" 16-GB DDR4 RDIMMs, and that it will also offer a 32-GB module; and Samsung, Micron and other companies already offer smaller-denomination DIMMs that comply with the spec.

Lower Power

The DDR4 spec defines memory that operates on 1.2V, compared with DDR3's 1.5V and 1.35V low-voltage spec. According to Samsung, its DDR4 RDIMMs consume about 40 percent less power than DDR3 memory modules operating at 1.35V. We're not sure what math they used to arrive at that finding, but in a world increasingly mindful of power consumption and rising energy costs, 1.2V is better than 1.35V.

More, Wider Memory

While DDR3 supported DIMM sizes between 512 MB and 8 GB in as many as eight banks, DDR4 quadruples memory top-end by doubling the module maximum to 16 GB (with a 2-GB minimum) in as many as 16 banks. That's math we can handle. What's more, DDR4 can arrange memory banks into as many as four groups, providing faster burst access to memory and separate read, write, activation and refresh operations for each group.

Incidentally, memory speeds of DDR4 will start at 1,600MHz and balloon to 3,200MHz. DDR3 mobiles are available mostly at frequencies between 800MHz and 1,600MHz, although the spec supports 1,866MHz and 2,133MHz memory, according to a comparison chart published by memory maker Micron.

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Refreshing DDR SDRAM

Internally, computer memory is arranged as a matrix of "memory cells" in rows and columns, like the squares on a checkerboard, with each column being further divided by the I/O width of the memory chip. The entire organization of rows and columns is called a DRAM "array." For example, a 2Mx8 DRAM has roughly 2000 rows , 1000 columns, and 8 bits per column -- a total capacity of 16Mb, or 16 million bits.

Each memory cell is used to store a bit of data - stored as an electrical charge - which can be instantaneously retrieved by indicating the data's row and column location; however, DRAM is a volatile form of memory, which means that it must have power in order to retain data. When the power is turned off, data in RAM is lost.

DRAM is called "dynamic" RAM because it must be refreshed, or re-energized, hundreds of times each second in order to retain data. It has to be refreshed because its memory cells are designed around tiny capacitors that store electrical charges. These capacitors work like very tiny batteries and will gradually lose their stored charges if they are not re-energized. Also, the process of retrieving, or reading, data from the memory array tends to drain these charges, so the memory cells must be precharged before reading the data.

Refresh is the process of recharging, or re-energizing, the cells in a memory chip. Cells are refreshed one row at a time (usually one row per refresh cycle). The term "refresh rate" refers, not to the time it takes to refresh the memory, but to the total number of rows that it takes to refresh the entire DRAM array -- e.g. 2000 (2K) or 4000 (4K) rows. The term "refresh cycle" refers to the time it takes to refresh one row or, alternatively, to the time it takes to refresh the entire DRAM array. Refresh can be accomplished in many different ways, which is one of the reasons it can be a confusing topic.

Why are there different types of refresh? How are they different?
Refresh rate is determined by the total number of rows that have to be refreshed in a memory chip. Memory chips are designed for a particular type of refresh. For example, chips using 4K refresh will have about 4000 rows, which means that it will take about 4000 cycles to refresh the entire array. Chips using 2K refresh will have about 2000 rows, and chips with 1K refresh will have about 1000 rows. All of the chips in the chart below have the same total capacity* (16Mb, or 16 million cells), but different numbers of rows and columns depending on the type of refresh used.

	4K refresh	2K refresh	1K refresh
4Mx4	4000 rows / 1000 columns	2000 rows / 2000 columns
2Mx8	4000 rows / 500 columns	2000 rows / 1000 columns
1Mx16	4000 rows / 250 columns		1000 rows / 1000 columns

* Capacity = rows x columns x width. For example, a 4Mx4 chip is 4 Megabits "deep" and 4 bits "wide" (Total = 16Mb). If this chip uses 4K refresh, it will be organized into 4000 rows x 1000 columns x 4 bits per column (Total = 16Mb). If this chip uses 2K refresh, it will be internally organized into 2000 rows x 2000 columns x 4 bits per column (Total = 16Mb). The capacity is the same, but the organization and refresh are different.

The major refresh rates in use today are 1K, 2K, 4K, and 8K. The primary reason for these different types of refresh is decreased power consumption. Since column address circuitry requires more power than row address circuitry, using a type of refresh that selects fewer columns per row draws less current -- e.g. 4K versus 2K.

In addition to various refresh rates, there are several different refresh methods. The two most basic methods are distributed and burst. Distributed refresh charges one row at a time, in sequential order. Burst refresh charges a whole group of rows in one burst.

Normally, the refresh operation is initiated by the system's memory controller, but some chips are designed for "self refresh." This means that the DRAM chip has its own refresh circuitry and does not require intervention from the CPU or external refresh circuitry. Self refresh dramatically reduces power consumption and is often used in portable computers.

Two other refresh techniques are hidden and extended refresh. Both of these techniques rely on capacitors (memory cells) that discharge more slowly. Hidden refresh combines the refresh operation with read/write operations. Extended refresh extends the length of time it takes to refresh the entire memory array. The advantage of both is that they do not have to refresh as often.

Why does 4K refresh consume less power than 2K refresh?
It seems logical to think that 4K refresh would consume more power than 2K refresh because the number is larger, but that is not the case. The numbers do not refer to the size of the refresh area but to the number of rows that it takes to refresh the entire DRAM. 2K refresh charges about 2000 rows to refresh a DRAM chip; 4K refresh charges twice as many rows. The tradeoff is that while 4K refresh takes longer, it consumes less power.

In actuality, 4K refresh charges a smaller section of the total array per cycle than 2K refresh. Looking at the chart above, you can see a 4Mx4 chip with 4K refresh charges about 1000 columns for every row, but the same chip with 2K refresh charges about 2000 columns for every row. Remember that column address circuitry requires more power than row address circuitry, so a refresh that charges fewer columns per row draws less current. 4K refresh charges fewer columns per row than 2K refresh and therefore uses less power -- about 1.2x less power.

Is the performance any different for one type of refresh versus another?
Performance differences are miniscule, but a 2K version of one DRAM chip will perform slightly better than a 4K version. The tradeoff between the number of rows and columns in the internal organization affects what is known as the "page depth" of the DRAM chip, which can impact particular applications. On the other hand, a 4K chip consumes much less power. Deciding which type of refresh to use depends on the specific system and application. These specifications are usually detailed by the system manufacturers.

Where are the different types of refresh used?
Most memory chips today use 1K or 2K refresh and can be found in the majority of PCs. At first, 4K refresh was used in portables, workstations, and PC servers because it consumes less power and generates less heat, but 4K refresh is also increasing in desktop PCs. 8K refresh is fairly new and is exclusive to 64Mb chips at present (mostly high-end applications).

Is memory with different refresh rates interchangeable?
The memory controller in your system determines the type of refresh it can support. Some controllers have only enough drivers to support 2K refresh (2000 rows). Others have been designed to support both types of refresh (2K and 4K) using a technique called "redundant addressing." Some support only 4K refresh. It all depends on the system itself.